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參數(shù)資料
| 型號： | TDA8924TH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 2 x 120 W class-D power amplifier |
| 中文描述： | 120 W, 2 CHANNEL, AUDIO AMPLIFIER, PDSO24 |
| 封裝： | PLASTIC, SOT-566-3, HSOP-24 |
| 文件頁數(shù)： | 15/35頁 |
| 文件大小： | 722K |
| 代理商： | TDA8924TH |
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2003 Jul 28
15
Philips Semiconductors
Objective specification
2
×
120 W class-D power amplifier
TDA8924
16 APPLICATION INFORMATION
16.1
BTL application
When using the power amplifier in a mono BTL application
(for more output power), the inputs of both channels must
be connected in parallel; the phase of one of the inputs
must be inverted; see Fig.5. In principle the loudspeaker
can be connected between the outputs of the two
single-ended demodulation filters.
16.2
Pin MODE
For correct operation the switching voltage at pin MODE
should be debounced. If pin MODE is driven by a
mechanical switch an appropriate debouncing low-pass
filtershouldbeused.IfpinMODEisdrivenbyanelectronic
circuit or microcontroller then it should remain at the mute
voltage level for at least 100 ms before switching back to
the standby voltage level.
16.3
Output power estimation
The output power in several applications (SE and BTL)
can be estimated using the following expressions:
SE:
Maximum current:
should not exceed 12 A.
BTL:
Maximum current:
should not exceed 12 A.
Legend:
R
L
= load impedance
f
osc
= oscillator frequency
t
min
= minimum pulse width (typical 190 ns)
V
P
= single-sided supply voltage (so if supply
±
30 V
symmetrical, then V
P
= 30 V)
P
o(1%)
= output power just at clipping
P
o(10%)
= output power at THD = 10 %
P
o(10%)
= 1.25
×
P
o(1%)
.
16.4
External clock
The minimum required symmetrical supply voltage for
external clock application is
±
15 V (equally, the minimum
asymmetrical supply voltage for applications with an
external clock is 30 V).
When using an external clock the duty cycle of the external
clock has to be between 47.5 % and 52.5 %.
A possible solution for an external clock oscillator circuit is
illustrated in Fig.7.
P
o(1%)
R
-----------------------------------------------------------------------------------------
0.6
R
V
P
1
t
min
f
osc
×
–
(
)
×
×
2
2
R
L
×
=
I
o(peak)
V
--------------R
1
L
t
min
0.6
+
f
osc
×
–
(
)
×
=
P
o(1%)
R
---------------------------------------------------------------------------------------------
1.2
R
2V
P
1
t
min
f
osc
×
–
(
)
×
×
2
2
R
L
×
=
I
o(peak)
2V
--------------------------------------------f
1
t
1.2
+
osc
R
L
)
=
handbook, full pagewidth
1
14
7
2
11
13
10
4
5
6
8
9
12
3
CTC
0
0
+
ASTAB
ASTAB
+
TRIGGER
+
TRIGGER
RETRIGGER
MR
220
nF
5.6 V
4.3 V
HOP
GND
MBL468
HEF4047BT
VDD
360 kHz
320 kHz
VDDA
VSS
9.1 k
2 k
120 pF
RTC
CLOCK
RCTC
Fig.7 External oscillator circuit.
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