參數(shù)資料
型號: TDA9181T
廠商: NXP SEMICONDUCTORS
元件分類: 信號分離
英文描述: Integrated multistandard comb filter
中文描述: Y/C SEPARATOR IC, PDSO16
封裝: 7.50 MM, PLASTIC, MS-013, SOT162-1, SOP-16
文件頁數(shù): 8/32頁
文件大?。?/td> 135K
代理商: TDA9181T
2000 Nov 22
8
Philips Semiconductors
Objective specification
Integrated multistandard comb filter
TDA9181
CHARACTERISTICS
V
CCA
= V
DDD
= 5 V; T
amb
= 25
°
C; input signal Y/CVBS
1
= 1 V (p-p); input signal Y/CVBS
2
= 1 V (p-p); input signal
C
IN
= 0.7 V (p-p); input signal FSC = 200 mV (p-p) sine wave at f
SC
; input signal SC = 5 V (p-p) sandcastle signal; test
signal: 100/0/75/0 EBU colour bar for PAL B, G, H, D, I and N, 100% white 75% amplitude FCC colour bar for NTSC M
and PAL M; source impedance for Y/CVBS
1
and Y/CVBS
2
= 75
, coupled with 10 nF; source impedance for C
IN
and
FSC = 75
, coupled with 100 nF; load impedance for CVBS/Y
OUT
and C
OUT
= 15 pF to analog ground (pin AGND); all
voltages are related to analog ground (pin AGND); unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
V
CCA
I
CCA
V
DDD
I
DDD
P
analog supply voltage
analog supply current
digital supply voltage
digital supply current
power dissipation
4.5
4.5
5.0
25
5.0
10
175
5.5
5.5
V
mA
V
mA
mW
Luminance or CVBS input 1 and input 2; pins Y/CVBS
1
and Y/CVBS
2
V
i(Y/CVBS)(p-p)
luminance or CVBS input
voltage (peak-to-peak value)
clamp time constant
input current
including sync
0.7
1.0
1.4
V
t
clamp(Y/CVBS)
I
i(Y/CVBS)
10
10
20
0
0
+10
+10
lines
μ
A
nA
during clamping
during active video
Chrominance input; pin C
IN
V
i(CIN)(p-p)
chrominance input voltage
(peak-to-peak value)
input resistance
0.7
1.0
V
R
i(CIN)
Colour subcarrier input; pin FSC
30
k
V
i(FSC)(p-p)
subcarrier input voltage
(peak-to-peak value)
duty cycle
input resistance
100
200
400
mV
D
R
i(FSC)
Sandcastle input; pin SC
square wave
40
30
50
60
%
k
V
i(SC)
sandcastle input voltage
no clamping
clamping
clamping; note 1
with respect to end of
line-blanking; note 1
3.7
2.6
3.3
2.6
V
V
μ
s
μ
s
t
W
t
W(rep)
pulse width
pulse rising edge position
R
i(SC)
C
i(SC)
Input switch select input; pin INPSEL
input resistance
input capacitance
1
2
M
pF
V
IL
V
IH
R
i(INPSEL)
C
i(INPSEL)
LOW-level input voltage
HIGH-level input voltage
input resistance
input capacitance
Y/CVBS
1
selected
Y/CVBS
2
selected
2.0
100
0.5
2
V
V
k
pF
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