
Philips Semiconductors
Preliminary specification
1999 Sep 28
19
TV signal processor-Teletext decoder with
embedded
μ
-Controller
TDA 935X/6X/8X series
P3
-
-
-
-
P3<3>
P3<2>
P3<1>
P3<0>
FFH
P3<3:0>
Port 3 I/O register connected to external ADC pins. Any combination of ADC input or PWM (P3<3:0>) output available via Software control.
P0CFGA
-
P0CFGA<6>
P0CFGA<5>
-
-
-
-
-
FFH
P0CFGB
-
P0CFGB<6>
P0CFGB<5>
-
-
-
-
-
00H
P0CFGB<x>/P0CFGA<x> = 00
MODE 0 Open Drain
P0CFGB<x>/P0CFGA<x> = 01
MODE 1 Quasi Bi-Directional
P0CFGB<x>/P0CFGA<x> = 10
MODE2 High Impedance
P0CFGB<x>/P0CFGA<x> = 11
MODE3 Push Pull
P1CFGA
P1CFGA<7>
P1CFGA<6>
-
-
P1CFGA<3>
P1CFGA<2>
P1CFGA<1>
P1CFGA<0>
FFH
P1CFGB
P1CFGB<7>
P1CFGB<6>
-
-
P1CFGB<3>
P1CFGB<2>
P1CFGB<1>
P1CFGB<0>
00H
P1CFGB<x>/P1CFGA<x> = 00
MODE 0 Open Drain
P1CFGB<x>/P1CFGA<x> = 01
MODE 1 Quasi Bi-Directional
P1CFGB<x>/P1CFGA<x> = 10
MODE2 High Impedance
P1CFGB<x>/P1CFGA<x> = 11
MODE3 Push Pull
P2CFGA
-
-
-
-
-
-
-
P2CFGA<0>
FFH
P2CFGB
-
-
-
-
-
-
P2CFGB<0>
00H
P2CFGB<x>/P2CFGA<x> = 00
MODE 0 Open Drain
P2CFGB<x>/P2CFGA<x> = 01
MODE 1 Quasi Bi-Directional
P2CFGB<x>/P2CFGA<x> = 10
MODE2 High Impedance
P2CFGB<x>/P2CFGA<x> = 11
MODE3 Push Pull
P3CFGA
-
-
-
-
P3CFGA<3>
P3CFGA<2>
P3CFGA<1>
P3CFGA<0>
FFH
P3CFGB
-
-
-
-
P3CFGB<3>
P3CFGB<2>
P3CFGB<1>
P3CFGB<0>
00H
P3CFGB<x>/P3CFGA<x> = 00
MODE 0 Open Drain
P3CFGB<x>/P3CFGA<x> = 01
MODE 1 Quasi Bi-directional
P3CFGB<x>/P3CFGA<x> = 10
MODE2 High Impedance
P3CFGB<x>/P3CFGA<x> = 11
MODE3 Push Pull
PCON
-
ARD
RFI
WLE
GF1
GF0
PD
IDL
00H
ARD
Auxiliary RAM Disable, All MOVX instructions access the external data memory
RFI
Disable ALE during internal access to reduce Radio Frequency Interference
WLE
Watch Dog Timer enable
GF1
General purpose flag
GF0
General purpose flag
PD
Power-down activation bit
IDL
Idle mode activation bit
PSW
C
AC
F0
RS<1>
RS<0>
OV
-
P
00H
C
Carry Bit
AC
Auxiliary Carry bit
F0
Flag 0, General purpose flag
Names
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
Table 4 SFR Bit description