參數(shù)資料
型號(hào): TDA9852
廠商: NXP SEMICONDUCTORS
元件分類(lèi): 消費(fèi)家電
英文描述: I2C-bus controlled BTSC stereo/SAP decoder and audio processor
中文描述: SPECIALTY CONSUMER CIRCUIT, PDIP42
文件頁(yè)數(shù): 21/40頁(yè)
文件大?。?/td> 258K
代理商: TDA9852
1997 Mar 11
21
Philips Semiconductors
Preliminary specification
I
2
C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
I
2
C-bus format to write (slave receives data)
Table 4
Explanation of I
2
C-bus format to write (slave receives data)
If more than 1 byte of DATA is transmitted, then auto-increment is performed, starting from the transmitted subaddress
and auto-increment of subaddress in accordance with the order of Table 5 is performed.
Table 5
Subaddress second byte after MAD
Note
1.
In auto-increment mode it is necessary to insert 3 dummy data words between volume left and control 1.
Table 6
Definition of third byte, third byte after MAD and SAD
S
SLAVE ADDRESS
R/W
A
SUBADDRESS
A
DATA
A
P
NAME
DESCRIPTION
S
Standard SLAVE ADDRESS (MAD)
R/W
A
SUBADDRESS (SAD)
DATA
P
START condition
101 101 1
0 (write)
acknowledge; generated by the slave
see Table 5
see Table 6
STOP condition
FUNCTION
REGISTER
MSB
LSB
D7
D6
D5
D4
D3
D2
D1
D0
Volume right
Volume left
Control 1 (note 1)
Control 2
Control 3
Alignment 1
Alignment 2
Alignment 3
VR
VL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
1
0
0
0
0
0
0
1
1
0
0
1
0
1
1
0
1
0
1
0
CON1
CON2
CON3
ALI1
ALI2
ALI3
FUNCTION
REGISTER
MSB
LSB
D7
D6
D5
D4
D3
D2
D1
D0
Volume right
Volume left
Control 1
Control 2
Control 3
Alignment 1
Alignment 2
Alignment 3
VR
VL
0
0
VR6
VL6
AVLON
STEREO
0
0
0
AT1
VR5
VL5
LOFF
TZCM
0
0
0
AT2
VR4
VL4
CCD
1
0
A14
A24
0
VR3
VL3
0
LMU
L3
A13
A23
1
VR2
VL2
SC2
EF2
L2
A12
A22
TC2
VR1
VL1
SC1
EF1
L1
A11
A21
TC1
VR0
VL0
SC0
EF0
L0
A10
A20
TC0
CON1
CON2
CON3
ALI1
ALI2
ALI3
GMU
SAP
0
0
STS
ADJ
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