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參數(shù)資料
| 型號： | TDA9855WP |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | I2C-bus controlled BTSC stereo/SAP decoder and audio processor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC68 |
| 文件頁數(shù)： | 21/52頁 |
| 文件大?。?/td> | 345K |
| 代理商： | TDA9855WP |
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1997 Nov 04
21
Philips Semiconductors
Product specification
I
2
C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9855
Notes to the characteristics
1.
The oscillator is designed to operate together with a MURATA resonator CSB503F58 for TDA9855. Change of the
resonator supplier is possible, but the resonator specification must be close to CSB503F58 for TDA9855.
2.
The internal SAP carrier level is determined by the composite input level and the level adjustment gain.
3.
Select in to input line control.
4.
Crosstalk:
5.
The transmission contains:
a) Total initialization with MAD and SAD for volume and 11 DATA words, see also definition of characteristics
b) Clock frequency = 50 kHz
c) Repetition burst rate = 400 Hz
d) Maximum bus signal amplitude = 5 V (p-p).
The listed pin voltage corresponds with typical gain steps of +6 dB, +3 dB, 0 dB,
6 dB and
15 dB.
Attack time constant = C
AV
×
R
att
.
6.
7.
8.
Example: C
AV
= 4.7
μ
F; I
dec
= 2
μ
A; G
v1
=
9 dB; G
v2
= +6 dB
→
decay time results in 4.14 s.
When reset is active the GMU-bit (general mute) and the LMU-bit (LINE OUT mute) is set and the I
2
C-bus receiver
is in the reset position.
10. The AC characteristics are in accordance with the I
2
C-bus specification. The maximum clock frequency is 100 kHz.
Information about the I
2
C-bus can be found in the brochure “The I
2
C-bus and how to use it”
(order number 9398 393 40011).
9.
20 logV
V
o(rms)
--------------------
Decay time
C
AV
-----------------------------------------------------------------------------------
0.76 V
×
10
G
v1
20
–
------------
10
G
v2
20
–
------------
–
I
dec
=
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