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參數(shù)資料
| 型號： | TDA9901TS/C3,118 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 18/18頁 |
| 文件大小： | 0K |
| 描述： | IC AMP DIFF WIDEBAND 20-SSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 放大器類型： | 可變增益 |
| 電路數(shù)： | 1 |
| 輸出類型： | 差分 |
| -3db帶寬： | 130MHz |
| 電流 - 輸入偏壓： | 55µA |
| 電流 - 電源： | 30mA |
| 電流 - 輸出 / 通道： | 10mA |
| 電壓 - 電源，單路/雙路(±)： | 4.75 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-LSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 935276628118 TDA9901TS/C3-T TDA9901TS/C3-T-ND |
TDA9901_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 14 August 2008
9 of 18
NXP Semiconductors
TDA9901
Wideband differential digital controlled variable gain amplier
[1]
Due to the behavior of the on-chip regulator a warm-up time of 1 minute (typical) is recommended for optimal performance.
[2]
The analog output voltages are positive with respect to VSSA.
[3]
In latching mode (pin TE LOW), the gain settling is latched at the rising edge of the clock input.
[4]
In transparent mode, the gain settling is directly controlled by the input data pattern.
[5]
The circuit may be used with a single TTL clock on CLK or CLKN. The unused clock pin has to be decoupled to ground with a 100 nF
capacitance.
[6]
There are four modes of operation for the clock inputs in non-TTL mode:
a) PECL mode 1: (DC level vary 1 : 1 with VDDA) CLK and CLKN inputs are differential PECL levels.
b) PECL mode 2: (DC level vary 1 : 1 with VDDA) CLK input is at PECL level and gain change takes place on the rising edge of the clock
input signal when in latched mode. A DC level of 3.65 V has to be applied on CLKN decoupled to VSSD via a 100 nF capacitor.
c) PECL mode 3: (DC level vary 1 : 1 with VDDA) CLKN input is at PECL level and gain change takes place on the rising edge of the
clock input signal when in latched mode. A DC level of 3.65 V has to be applied on CLK decoupled to VSSD via a 100 nF capacitor.
d) AC driving mode 4: when driving the CLK input directly and with any AC signal of minimum 0.1 V (p-p) and with a DC level of 2.5 V,
the gain change takes place on the rising edge of the clock signal. When driving the CLKN input with the same signal, gain change
takes place on the falling edge of the clock signal. NXP Semiconductors recommends decoupling of the CLKN or CLK input to VSSD
via a 100 nF capacitor.
tr
rise time
-
4.0
-
ns
tf
fall time
-
4.0
-
ns
Digital inputs: pins TE, GRAY0, GRAY1 and GRAY2
VIL
LOW-level input voltage
0
-
0.8
V
VIH
HIGH-level input voltage
2.0
-
VDDD
V
IIH
HIGH-level input current
10
-
+10
A
IIL
LOW-level input current
10
-
+10
A
Ci
input capacitance
-
3
pF
Clock inputs in TTL mode
VIL
LOW-level input voltage
[5] 0
-
0.8
V
VIH
HIGH-level input voltage
[5] 2.0
-
VDDD
V
IIH
HIGH-level input current
15
-
80
A
IIL
LOW-level input current
40
-
10
A
Ci
input capacitance
-
2
pF
Clock inputs in differential mode
VIL
LOW-level input voltage
VDDA = 5.0 V
[6] 3.19
-
3.52
V
VIH
HIGH-level input voltage VDDA = 5.0 V
[6] 3.83
-
4.12
V
IIH
HIGH-level input current
15
-
80
A
IIL
LOW-level input current
40
-
5
A
Ci
input capacitance
-
2
pF
Vi(dif)(p-p)
peak-to-peak differential
input voltage
DC voltage level = 2.5 V
0.1
-
2.0
V
Table 6.
Characteristics …continued
VDDA = V11 to V12 = 4.75 V to 5.25 V; VDDD = V18 to V17 = 3.0 V to 5.25 V; VSSA and VSSD shorted together;
Tamb = 40 °C to +85 °C; typical values measured at VCCA = 5.0 V; VCCD = 3.3 V and Tamb =25 °C unless otherwise specied
[1].
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
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