參數(shù)資料
型號: TDA9964HL
廠商: NXP SEMICONDUCTORS
元件分類: ADC
英文描述: 12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras
中文描述: 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48
文件頁數(shù): 14/24頁
文件大?。?/td> 109K
代理商: TDA9964HL
2000 May 02
14
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 30 Msps analog-to-digital
interface for CCD cameras
TDA9964
Table 1
Serial interface programming
Table 2
Polarity settings
Table 3
Standby control using pin STDBY
Table 4
Output enable selection using output enable pin (OE)
ADDRESS BITS
DATA BITS D9 TO D0
A3
A2
A1
A0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
PGA gain control (SD7 to SD0)
DAC OFDOUT output control (SD7 to SD0)
ADC clamp reference control (SD6 to SD0); from code 0 to 127
control pulses (pins SHP, SHD, CLPDM, CLPOB, BLK and CLK) polarity settings;
SD2, SD6, SD7 and SD9 should be set to logic 1; for SD6 and SD7 see Tables 3 4, 5, and 6
SD7 = 0 by default; SD7 = 1 PGA gain up to 36 dB but noise and clamp behaviour are not
guaranteed
initialization (SD8 = 1; SD11 to SD9 = 0 and SD7 to SD0 = 0)
test modes
0
1
0
0
1
1
1
1
other addresses
SYMBOL
PIN
SERIAL CONTROL BIT
ACTIVE EDGE OR LEVEL
SHP and SHD
CLK
CLPDM
CLPOB
BLK
VSYNC
45 and 46
47
48
44
43
20
SD4
SD5
SD0
SD1
SD3
SD8
1 = HIGH; 0 = LOW
1 = rising; 0 = falling
1 = HIGH; 0 = LOW
1 = HIGH; 0 = LOW
1 = HIGH; 0 = LOW
0 = rising; 1 = falling
BIT SD7 OF
REGISTER 0011
STDBY
ADC DIGITAL OUTPUTS D11 TO D0
I
CCA
+ I
CCO
+ I
CCD
(typ.)
1
1
0
1
0
last logic state
active
active
test logic state
1.5 mA
72 mA
72 mA
1.5 mA
0
BIT SD6 OF
REGISTER 0011
OE
ADC DIGITAL OUTPUTS D11 TO D0
1
0
1
0
1
active, binary
high impedance
high impedance
active binary
0
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