參數(shù)資料
型號(hào)： TDA9965A
廠商： NXP Semiconductors N.V.
英文描述： 12-bit, 5.0 V, 40 Msps analog-to-digital interface for CCD cameras
中文描述： 12位，5.0 V固定，40 Msps的模擬到數(shù)字的CCD相機(jī)接口
文件頁(yè)數(shù)： 11/22頁(yè)
文件大小： 136K
代理商： TDA9965A
2004 Jul 05
11
Philips Semiconductors
Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras
TDA9965A
Table 1
Serial interface programming
Notes
1.
2.
PGA gain register must always be refreshed after clamp code register content has been changed.
When pin CLPADC = HIGH (SD1 = 1; serial interface), the ADC input is clamped to the voltage level of V
ref
. Pin V
ref
is connected to ground via a capacitor.
When the power supplies increase from zero to V
CC
, the init-on-power block initializes the circuit as follows:
Cut-off frequency of the CTH circuit is set to: code f
co(CTH)
= 0
PGA gain control is set to: code G
PGA
= 0
Clamp code of the ADC is set to: code ADC
CLP
= 0
SHP and SHD sample on HIGH level; CLKADC activated with rising edge
CLPOB and CLPADC activated on HIGH level.
Table 2
Standby selection
Note
1.
If an external regulator is used it has to be switched off in standby mode in order to avoid extra power consumption
by the TDA9965A.
ADDRESS BITS
SDATA BITS SD0 to SD9
A1
A0
0
0
1
1
0
1
0
1
clamp reference of ADC (SD0 to SD9); note 1
cut-off frequency of CTH (SD0 to SD3)
PGA gain control (SD0 to SD9)
edge control for pulses SHP, SHD, CLPOB, CLPADC and CLKADC (note 2):
SD0 = 1, SHP and SHD sample on LOW level
SD1 = 1, CLPADC and CLPOB activated on HIGH level
SD2 = 1, CLKADC activated with rising edge
PIN STDBY
DATA BITS SD9 to SD0
I
CCA
+ I
CCD
4 mA (typical); note 1
84 mA (typical)
HIGH
LOW
logic 0
active
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參數(shù)描述
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