2002 May 14
5
Philips Semiconductors
Product specification
0.95 V starting DC-to-DC converter
with low battery indicator
TEA1200TS
PINNING
SYMBOL
PIN
DESCRIPTION
LX1
SHDWN0
1
2
inductor connection 1
DC-to-DC converter shut-down
input
up mode: DC-to-DC converter
output; down mode DC-to-DC
converter input
up mode: DC-to-DC converter
output; down mode DC-to-DC
converter input
current limiting resistor
connection
not connected
reference voltage input
internal supply ground
low battery detector input 1
low battery detector output
reference voltage input
DC-to-DC converter feedback
input
DC-to-DC converter ground
synchronization clock input or
PWM-only selection input
conversion mode selection input
inductor connection 2
UPOUT/DNIN
3
UPOUT/DNIN
4
ILIM
5
n.c.
V
ref
GND
LBI1
LBO
V
ref
FB0
6
7
8
9
10
11
12
GND0
SYNC/PWM
13
14
U/D
LX2
15
16
handbook, halfpage
TEA1200TS
MBL419
1
2
3
4
5
6
7
8
LX1
SHDWN0
UPOUT/DNIN
UPOUT/DNIN
ILIM
n.c.
Vref
GND
LX2
U/D
SYNC/PWM
GND0
FB0
Vref
LBO
LBI1
16
15
14
13
12
11
10
9
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
Control mechanism
The TEA1200TS DC-to-DC converter is able to operate in
the PFM (discontinuous conduction) or PWM (continuous
conduction) operating mode. All switching actions are
completely determined by a digital control circuit which
usestheoutputvoltagelevelasitscontrolinput.Thisnovel
digital approach enables the use of a new pulse width and
frequency modulation scheme, which ensures optimum
power efficiency over the complete range of operation of
the converter.
When high output power is requested, the device will
operate in the PWM operating mode. This results in
minimumAC currentsinthecircuitcomponentsandhence
optimum efficiency, minimum costs and low EMC. In this
operating mode, the output voltage is allowed to vary
between two predefined voltage levels. As long as the
output voltage stays within this so-called window,
switching continues in a fixed pattern.
When the output voltage reaches one of the window
borders, the digital controller immediately reacts by
adjusting the pulse width and inserting a current step in
such a way that the output voltage stays within the window
with higher or lower current capability. This approach
enables very fast reaction to load variations. Figure 3
shows the response of the converter to a sudden load
increase. The upper trace shows the output voltage.
The ripple on top of the DC level is a result of the current
in the output capacitor, which changes in sign twice per
cycle, times the internal Equivalent Series Resistance
(ESR) of the capacitor. After each ramp-down of the
inductor current, i.e. when the ESR effect increases the
output voltage, the converter determines what to do in the
next cycle. As soon as more load current is taken from the
output the output voltage starts to decay.