參數(shù)資料
型號: TEA6320T-T
廠商: NXP SEMICONDUCTORS
元件分類: 音頻控制
英文描述: 2 CHANNEL(S), SOUND FADER CONTROL CIRCUIT, PDSO32
文件頁數(shù): 2/40頁
文件大?。?/td> 188K
代理商: TEA6320T-T
1995 Dec 19
10
Philips Semiconductors
Preliminary specication
Sound fader control circuit
TEA6320
Notes to the characteristics
1. The indicated values for output power assume a 6 W power amplifier at 4
with 20 dB gain and a fixed attenuator
of 12 dB in front of it. Signal-to-noise ratios exclude noise contribution of the power amplifier.
2. The transmission contains: total initialization with MAD and subaddress for volume and 8 data words, see also
definition of characteristics, clock frequency = 50 kHz, repetition burst rate = 400 Hz, maximum bus signal
amplitude = 5 V (p-p).
3. The AC characteristics are in accordance with the I2C-bus specification. This specification,
“The I2C-bus and how to
use it”, can be ordered using the code 9398 393 40011.
Mute function (see Fig.10)
HARDWARE MUTE
Vsw
mute switch level (2
× VBE)
1.45
V
mute active
VswLOW
input level
1.0
V
Ii
input current
VswLOW =1V
300
A
mute passive: level internally dened
VswHIGH
saturation voltage
VCC
V
td(mute)
delay until mute passive
0.5
ms
ZERO CROSSING MUTE
Id
discharge current
0.3
0.6
1.2
A
Ich
charge current
300
150
A
VswDEL
delay switch level (3
× VBE)
2.2
V
td
delay time
Cm =10nF
100
ms
Vwind
window for audio signal zero
crossing detection
30
40
mV
Muting at power supply drop
VCCdrop
supply drop for mute active
V19
0.7
V
Power-on reset (when reset is active the GMU-bit (general mute) is set and the I2C-bus receiver is in
reset position)
VCC
increasing supply voltage start of
reset
2.5
V
end of reset
5.2
6.5
7.2
V
decreasing supply voltage start of
reset
4.2
5.5
6.2
V
Digital part (I2C-bus pins); note 3
ViH
HIGH level input voltage
3
9.5
V
ViL
LOW level input voltage
0.3
+1.5
V
IiH
HIGH level input current
10
+10
A
IiL
LOW level input current
10
+10
A
VoL
LOW level output voltage
IL =3mA
0.4
V
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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