參數(shù)資料
型號： TFA9812HN/N1,518
廠商： NXP SEMICONDUCTORS
元件分類： 音頻／視頻放大
英文描述： 15 W, 2 CHANNEL, AUDIO AMPLIFIER, PQCC48
封裝： 7 X 7 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT619-8, HVQFN-48
文件頁數(shù)： 2/66頁
文件大小： 386K
代理商： TFA9812HN/N1,518
TFA9812_2
NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 22 January 2009
10 of 66
NXP Semiconductors
TFA9812
BTL stereo Class-D audio amplier with I2S input
In Soft mute mode the I2S input signal is overruled with a soft mute.
– In Legacy control mode the analog input pin AVOL controls Soft mute mode.
– In I2C control mode I2C control can be used to enable an automatic soft mute
function. See also Section 8.5.3.
In Hard mute mode the PWM controller is overruled with a 50 % duty cycle square
pulse. The Hard mute mode is only available in I2C control mode.
In Operating mode the TFA9812 amplies the I2S audio input signal in line with the
actual control setting.
In 3-state mode the output stages are switched off.
Fault mode is entered when a fault condition is detected by one or more of the
protection mechanisms implemented in the TFA9812. In Fault mode the actual device
conguration depends on the fault detected: see Section 8.7 for more information.
Fault mode is for a subset of the faults agged on the DIAG output pin. When the
DIAG pin is agged the output stages will be forced to enter 3-state mode. In Sleep
mode the DIAG pin will not ag fault modes.
[1]
Clocking faults do not trigger DIAG output.
[2]
Under these conditions soft mute still has to be enabled by the appropriate I2C setting.
8.2.3 I2S master/slave modes and MCLK/BCK clock modes
The I2S interface can be set in master or in slave.
In I2S master mode the PLL locks to the output signal of the internal crystal oscillator
circuit which uses an external crystal. The BCK, WS and MCLK signals are generated
by the TFA9812. On the MCLK pin the TFA9812 delivers a master clock running at the
crystal frequency.
In I2S slave mode the PLL can lock to:
– The external MCLK signal on the MCLK pin called MCLK clock mode.
– The I2S input BCK signal on the BCK pin called BCK clock mode.
The I2S master or slave mode can be selected:
In I2C control mode by selecting the right I2C setting.
In legacy control mode by selecting the right setting on the SDA/MS pin.
Table 5.
Operational mode selection
Pin:
DIAG Output
Operational mode
selected:
POWERUP
ENABLE
CSEL
AVOL
0
-
oating
Sleep mode
1
-
0 / oating
Fault mode (enabled by
1
-
oating
Soft mute mode (in I2C
control mode)[2]
1
0
< 0.8 V
oating
Soft mute (in Legacy control
mode)
1
0
-
oating
3-state mode
1
-
oating
Operational mode
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