參數(shù)資料
型號： TFA9812HN
廠商： NXP SEMICONDUCTORS
元件分類： 音頻／視頻放大
英文描述： 15 W, 2 CHANNEL, AUDIO AMPLIFIER, PQCC48
封裝： 7 X 7 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT619-8, HVQFN-48
文件頁數(shù)： 19/66頁
文件大?。?/td> 386K
代理商： TFA9812HN
TFA9812_2
NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 22 January 2009
26 of 66
NXP Semiconductors
TFA9812
BTL stereo Class-D audio amplier with I2S input
8.7.11 Invalid BCK protection
The BCK clock signal is veried as being at one of the allowed relative frequencies: 32 fs,
48 fs or 64 fs. If it is not at one of these frequencies the TFA9812 will set the output stages
to 3-state mode to prevent audible effects.
The MCLK clock signal is also veried as being valid, see Section 8.2.3.
Detection of violation results in an automatic internal overruling of the MCLK assignment
to BCK.
8.7.12 DC blocking
The TFA9812 features a high pass lter after the I2S input to block DC signals. DC values
at the output can damage the peripheral devices. The high pass lter is always enabled.
8.7.13 Overview protections
Table 21 shows the overview of the protections.
Table 21.
Overview protections
Protections
Symbol Conditions
DIAG
pin
I2C
ag[1]
Output
Recovering
TF
programmable
max. Tj > 125 °C
Floating
-
Switching
Automatic, increasing
volume control back to
volume setting
OTP
Tj > 160 °C
LOW
DIAG
Floating
Automatic, after 1
s and
Tj < 160 °C
OCP
IO > IORM
LOW
DIAG
Floating
Automatic, after 1
s and
IO <IORM
OVP
VDDA > 20 V
LOW
DIAG
Floating
Restart (fault to operating
when VDDA > 8 V and
VDDA(3V3) >3V)
UVP
VDDA < 8 V or
VDDA(3V3) <3V
LOW
DIAG
Floating
Restart (fault to operating
when VDDA > 8 V and
VDDA(3V3) >3V)
ODP
Tj > 140 °C and IO >IORM
LOW
DIAG
Floating
Restart (fault to operating
when Tj < 140 °C or
IO < IORM)
WP[2]
OUTX > VDDA 1 V or
OUTX < REFA + 1 V
LOW
DIAG
Floating
Restart (fault to operating
when OUTX < VDDA 1V
and OUTX > VSSA +1V)
LP
PLL out of lock
Floating
LP
Floating
Restart (fault to operating
when PLL is in lock)
UFP
PLL frequency < 45 MHz
Floating
UFP
Floating
Restart (fault to operating
when
PLL frequency > 45 MHz)
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