參數(shù)資料
型號(hào)： TFP6424PAP
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, THERMALLY ENHANCED, POWER, PLASTIC, TQFP-64
文件頁(yè)數(shù)： 8/65頁(yè)
文件大?。?/td> 813K
代理商： TFP6424PAP
TFP6422, TFP6424
PanelBus
DIGITAL TRANSMITTER/VIDEO ENCODER COMBO
SLDS118 – MARCH 2000
16
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
scaling processor (continued)
The Scaling Processor is enabled when the video output mode is one of the TV output modes (VIDOUT[3:0]
= 0001 through 0101) and the video input is progressive (FMT[[3:0] = any value other than 1000, 1001, 1100
and 1101).
Vertical scaling ratio registers VRATIOQ, VRATIOR, VRATIOQ2 and VRATIOR2 control the vertical scaling
ratio. The proper values of the vertical scaling ratio registers are computed as a function of the number of lines
from the input frame (defined in FLENS registers) and the number of the lines in the desired output frame
(defined in FLEN registers). Arbitrary scaling ratio from 0.5 to 1.0 is supported. Refer to the description of the
vertical scaling ratio registers for details.
VFLTR_CTRL register controls the filter characteristics of the vertical filter. The vertical filter performs both the
vertical interpolation and deflicker filtering. INPT bit determines whether the nearest neighboring interpolated
pixel (zero phase) or the interpolated dynamically adjusted pixel is to be used. The bandwidth of the vertical
filter is also programmable. DEFLKR[2:0] defines the filter bandwidth, which ranges from near all–pass to a very
narrow band. When selecting the bandwidth for an application, users must consider the trade–off between the
sharpness of the image and the amount of flickers present in the image.
Refer to the description of
VFLTR_CTRL for details.
Horizontal scaling process is determined by the desired number of pixels in an input scan line and the nominal
number of pixels in a scan line in the output frame. The desired number of pixels in a scan line is defined by
the LLEN registers, while the nominal number of pixels in a scan line is determined by the SQP bit and FFRQ
bit. See the description of BSTAMP register for details. The nominal number of pixels in a scan line determines
the default video encoding timing when horizontal scaling is disabled. When horizontal scaling is enabled, an
internal horizontal scaling ratio is computed and the internal video encoding time base is adjusted to account
for the scaling ratio. The horizontal scaling also affects the subcarrier frequency and the close caption carrier
frequency due to the change of the video encoding clock frequency. Both frequencies must be scaled
proportionally in order to maintain the correct frequencies. Please refer to S_CARR and CC_CARR registers
for details.
Scaling process is also tightly coupled to the video encoding clock and the clock of the video port. The clocks
must be scaled precisely to guarantee correct operations. See Clock Generation for details.
clock generation
There are five clock signals in TFP6422/6424. XTALI/XTALO, CLKOUT, CLKIN0/CLKIN1, CLKENC and
TXC–/TXC+.
XTALI and XTALO are terminals for the 14.31818 MHz crystal. When TFP6422/6424 is in TV video output
modes, the on–chip PLL uses the 14.31818 MHz clock as a reference to generate CLKOUT and CLKENC.
CLKOUT is output to an external device such as a graphics controller. The external device then uses CLKOUT
as a reference and generates and outputs a clock signal back to the CLKIN0 and CLKIN1 pins on
TFP6422/6424. CLKIN0 and CLKIN1 clock out the video pixel and control to the TFP6422/6424 Video Port. The
clock connected to CLKIN0 and CLKIN1 can be differential or single–ended. When the clock is differential,
CLKIN0 is the positive side of the clock and CLKIN1 is the negative side. In the case of single–ended, the clock
connects to CLKIN0 and CLKIN1 is tied to VDDQ/2. CLKENC is an internal clock, thus not accessible externally.
It is used by the internal video encoder core to encode the TV video output signal. Depending on the
applications, it is also possible to connect CLKOUT directly to CLKIN0 signal.
PRODUCT
PREVIEW
相關(guān)PDF資料
PDF描述
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