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參數(shù)資料
| 型號： | TH7422BVWORNGD/T |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, CQCC84 |
| 封裝： | CERAMIC, J LEAD PACKAGE-84 |
| 文件頁數(shù)： | 18/20頁 |
| 文件大?。?/td> | 1116K |
| 代理商： | TH7422BVWORNGD/T |
- if RE is activated or always at high level (Timing Diagram Figure 2), each stored charge is transferred to the rea-
dout capacitance; this continuous readout mode is recommended for long integration time.
Qs conversion into voltage is supported by the readout stage capacitance, linked to a low output impedance ampli-
fier. This capacitance is reset at VDR bias, before each pixel readout operation (high level φR).
Due to the “Vidicon” read out mode, Qb level needs adjustment so as to provide enough carriers to sustain photocurrent
and dark current during the integration time. Pixel antiblooming is also resulting from “Vidicon mode” since photodiodes
cannot consume more electrons than Qb.
Antismearing (frame to frame antiblooming) efficiency depends on the photodiode reset conditions, reverse bias recovering
need a minimum Qb condition such as :
Qb>Clat .VD
where : - Clat is the individual lateral input node capacitance, Clat ~1.8 pF (including photodiode, bonding pads...)
where : -VD is the photodiode bias : VD=VN - 0.78VG1 - 8.7
7/20
TH7422B
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相關(guān)代理商/技術(shù)參數(shù) |
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