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參數(shù)資料
| 型號： | TH74KB22B.VWONGD/T |
| 廠商： | ATMEL CORP |
| 元件分類： | 模擬信號調理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, CQCC84 |
| 封裝： | WINDOWED, CERAMIC, J LEAD PACKAGE-84 |
| 文件頁數(shù)： | 16/20頁 |
| 文件大小： | 1116K |
| 代理商： | TH74KB22B.VWONGD/T |
PIN DESCRIPTION
Odd and Even channels are fully independent, therefore same pin function will be found on odd and even sides.
FPL
This is the preload injection stage electrical input. Each
ΦPL pulse down overfills preload storage capacitance with
electrons.
ΦPL is connected to a diode cathode which anode is internally tied to Vss.
VGL1 This is the preload stage skimming gate. Its bias determines the voltage up to which preload storage capacitance
will be biased. Thus it drives preload level.
VGL2 This is the storage capacitance grid bias. It determines the bottom voltage of preload storing well, while VGL1 deter-
mines its top level. Preload capacitance thus is charged up proportionately to (VGL2 -VGL1) bias difference.
FL1
This is the main register storage grid clock. Charges are stored under
ΦL1 when transfer is disabled (RE at low le-
vel).
ΦL1 is also used for lateral transfers to input nodes.
FL2
This is the main register transfer grid clock.
ΦL2 is used to isolate ΦL1 content during lateral transfers. The main re-
gister is beginning and ending with
ΦL2 which therefore controls main register access and outputs. ΦL2 is gated by
RE input, it is internally pulled down when RE is low, preventing transfers, preload injection, read out and isolating
each
ΦL1 well.
RE
This is the “Read Enable” input. When high, it allows
ΦL2 input connection to main register, when low, main register
corresponding grids are pulled down whatever
ΦL2 input level is.
This input helps to serially read out two or more multiplexors with one single
ΦL2 signal for all. Data are stored into
the main register as long as RE is low, thus read out can occur later on.
FX
This is the lateral transfer grid command. Lateral transfer is allowed when
ΦX is at high level. ΦX is common to all
input nodes, all photodiode information is collected at the same time.
VG1
This is the lateral input stage skimming grid bias. This grid determines photodiodes reset bias, always the same
from integration time to integration time. After photodiode reset (input node capacitance reset) extra charges leading
to overcrossing VG1 level are skimmed back into ΦL1 main register wells.
VN
This is the InGaAs photodiode common cathode bias. VN is available on odd and even side, however, both pins are
connected together, to photodiode substrate.
VGS
This is main register output grid bias. It is used to isolate read out capacitance from main register. It allows charges
to be read out when
ΦL2 is at low level.
5/20
TH7422B
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