
THMC10
REMOTE/LOCAL TEMPERATURE MONITOR
WITH SMBus INTERFACE
SLIS089 – DECEMBER 1999
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
external temperature sensor connections (DXP and DXN)
The DXP and DXN terminals are used to sense the remote temperature of either a microprocessor die or a
simple diode-connected transistor. Referring to Figure 6, the THMC10 has an internal state machine controlling
an analog MUX, an 8-bit A/D converter, plus 10-
A and 90-A nominal current sources. The analog MUX
switches between the THMC10’s internal temperature sensor and the external one connected to DXP and DXN.
This allows the use of only one 8-bit A/D converter, eliminating errors which would be present when using two
separate A/Ds. The THMC10 takes a VBE measurement at 100 A, then takes a VBE measurement at 10 A,
and subtracts the difference between the two sampled values. It then scales the resulting
VBE measurement
into a 2s complement, 8-bit binary format that is available over the SMBus interface (see Table 2). By using two
different current levels and a single diode-connected transistor to measure the
VBE, the absolute VBE is
canceled, and therefore no calibration is needed.
8–Bit A/D
Converter
DXP
Substrate
On-Chip Temp
Sensor
GND
VDD
10
90
A
Control
State
Machine
Analog
MUX
Remote
Die
Substrate
DXN
Remote
Temp
Sensor
(CPU)
THMC10
Front End
A
Figure 6. Temperature Measurement Block Diagram
external temperature sensor diagnostics (DXP and DXN)
The THMC10 provides diagnostic capabilities to allow detection of either an open external sensor or a shorted
external sensor. When DXP is shorted to GND or VDD, the THMC10 reports 127°C for the external temperature.
If the interrupt mask bit is not set in the configuration register, it asserts the ALERT terminal low and sets bit two
in the status register. When DXP is shorted to DXN, the THMC10 reports 0
°C for the external temperature and
no fault is reported. If any of the above conditions exceed a temperature limit, then a temperature limit error is
also indicated in the status register if the interrupt mask bit is not set.