參數(shù)資料
型號: THNCF128MMA
廠商: Toshiba Corporation
英文描述: The THNCFxxxxMA series CompactFlash card is a flash technology based with ATA interface flash memory card
中文描述: 該THNCFxxxxMA系列CF卡是閃存技術(shù),ATA接口卡的閃存
文件頁數(shù): 18/52頁
文件大?。?/td> 461K
代理商: THNCF128MMA
2001-09-05 18/52
THNCFxxxMAA Series
Preliminary version
2.Configuration and Status register (Address 202H)
This register is used for observing the state of the card.
bit7
bit6
CHGED
SIGCHG
Note: initial value: 00H
Name
R/W
Function
CHGED
(CARD->)
When CHGED bit is set to
1
, -STSCHG pin is held
L
at the condition of
SIGCHG bit set to
1
and the card configured for the I/O interface.
SIGCHG
(HOST->)
signal (-STSCHG pin). When the card is configured I/O card interface and this bit
is set
1
, -STSCHG pin is controlled by CHGED bit. If this bit is set to
0
,
-STSCHG pin is kept
H
.
IOIS8
(HOST->)
data bus (D7 to D0).
PWD
(HOST->)
this bit is reset to
0
, the card transfers to idle state (active mode). RRDY/BSY
bit on Pin Replacement Register becomes BUSY when this bit is changed.
RRDY/BSY will not become Ready until the power state requested has been
entered. This card automatically powers down when it is idle and powers back up
when it receives a command.
INTR
(CARD->)
available whether I/O card interface has been configured or not. This signal
remains true until the condition, which caused the interrupt request, has been
serviced. If the
IEN bit in the Device Control Register disables interrupts, this bit
is a zero.
bit5
IOIS8
bit4
0
bit3
0
bit2
PWD
bit
1
INTR
bit0
0
R
This bit indicates that CRDY/-BSY bit on Pin Replacement register is set to
1
.
R/W
This bit is set or reset by the host for enabling and disabling the status-change
R/W
The host sets this field to
1
when it can provide I/O cycles only with on 8 bit
R/W
When this bit is set to
1
, the card enters sleep state (Power Down mode). When
R
This bit indicates the internal state of the interrupt request. This bit state is
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