參數(shù)資料
型號(hào): THS1030CDWG4
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
封裝: GREEN, PLASTIC, SOIC-28
文件頁數(shù): 20/37頁
文件大小: 727K
代理商: THS1030CDWG4
THS1030
3V TO 5.5V, 10BIT, 30 MSPS
CMOS ANALOGTODIGITAL CONVERTER
SLAS243E NOVEMBER 1999 REVISED DECEMBER 2003
27
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
driving the internal reference buffer (top/bottom mode)
Figure 31 shows the load present on the REFTS and REFBS pins in top/bottom mode due to the internal
reference buffer only. The sample and hold must also be driven via these pins, which adds additional load.
AVDD
AGND
AVDD + REFTS + REFBS
REFTS
REFBS
RIN
14 k
Mode = AVDD
_
+
4
Figure 31. Equivalent Circuit of Inputs to Internal Reference Buffer
Equations for the currents flowing into REFTS and REFBS are:
I
IN
TS
+
3
REFTS
* AV
DD *
REFBS
4
R
IN
I
IN
BS
+
3
REFBS
* AV
DD *
REFTS
4
R
IN
These currents must be provided by the sources on REFTS and REFBS in addition to the requirements of driving
the sample and hold. Tolerance on these currents are
±50%.
driving REFTS and REFBS
C1
7 pF
AVDD
AGND
CLK
C2
0.6 pF
CSAMPLE
VLAST
REFTS
REFBS
Mode = AVDD
Internal
Reference
Buffer
_
+
Figure 32. Equivalent Circuit of REFTS and REFBS Inputs
This is essentially a combination of driving the ADC internal reference buffer (if in top/bottom mode) and also
driving a switched capacitor load like AIN, but with the sampling capacitor and CP2 on each pin now being 0.6 pF
and about 0.6 pF respectively.
(12)
(13)
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