參數(shù)資料
型號: THS12082QDA
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 2-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32
封裝: PLASTIC, TSSOP-32
文件頁數(shù): 18/42頁
文件大?。?/td> 840K
代理商: THS12082QDA
THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
25
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing and signal description of the THS12082 (continued)
write timing (using WR, WR-controlled)
Figure 14 shows the write-timing behavior when the WR(R/W) input is programmed as a write input WR only.
The input RD acts as the read input in this configuration. This timing is called WR-controlled because WR is
the last external signal of CS0, CS1, and WR that becomes valid.
90%
10%
tsu
th
D(0–11)
DATA_AV
10%
tw(WR)
tsu(CS)
th(CS)
CS0
CS1
WR
RD
Figure 14. Write Timing Diagram Using WR (WR-controlled)
write timing parameter using WR (WR-controlled)
PARAMETER
MIN
TYP
MAX
UNIT
tsu(CS)
Setup time, CS stable to last WR valid
0
ns
tsu
Setup time, data valid to first WR invalid
5
ns
th
Hold time, WR invalid to data invalid
2
ns
th(CS)
Hold time, WR invalid to CS change
5
ns
tw(WR)
Pulse duration, WR active
10
ns
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