參數(shù)資料
型號(hào): THS1209IDAG4
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 2-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32
封裝: GREEN, PLASTIC, TSSOP-32
文件頁(yè)數(shù): 16/33頁(yè)
文件大?。?/td> 312K
代理商: THS1209IDAG4
THS1209
SLAS288B – JULY 2000 – REVISED DECEMBER 2002
www.ti.com
23
Timing and Signal Description of the THS1209
The reading from the THS1209 and writing to the THS1209 is performed by using the chip select inputs (CS0, CS1),
the write input WR and the read input RD. The write input is configurable to a combined read/write input (R/W). This
is desired in cases where the connected processor consists of a combined read/write output signal (R/W). The two
chip select inputs can be used to interface easily to a processor.
Reading from the THS1209 takes place by an internal RDint signal, which is generated from the logical combination
of the external signals CS0, CS1 and RD (see Figure 4). This signal is then used to strobe the words out and to enable
the output buffers. The last external signal (either CS0, CS1 or RD) to become valid makes RDint active while the
write input (WR) is inactive. The first of those external signals going to its inactive state then deactivates RDint again.
Writing to the THS1209 takes place by an internal WRint signal, which is generated from the logical combination of
the external signals CS0, CS1 and WR. This signal is then used to strobe the control words into the control registers
0 and 1. The last external signal (either CS0, CS1 or WR) to become valid makes WRint active while the read input
(RD) is inactive. The first of those external signals going to its inactive state then deactivates WRint again.
RDint
WRint
Control/Data
Registers
CS0
CS1
RD
WR
Data Bits
Figure 28. Logical Combination of CS0, CS1, RD, and WR
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