參數(shù)資料
型號(hào): THS1209IDAR
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 2-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32
封裝: GREEN, PLASTIC, TSSOP-32
文件頁數(shù): 8/33頁
文件大?。?/td> 312K
代理商: THS1209IDAR
THS1209
SLAS288B – JULY 2000 – REVISED DECEMBER 2002
www.ti.com
16
Figure 26 shows the conversion timing when two analog input channels are selected. The maximum throughput rate
per channel is 4 MSPS in this mode. The data flow in the bottom of the figure shows the order the converted data
is available to the data bus. The SYNC signal is always active low if data of channel 1 is available to the data bus.
There is a certain timing relationship required for the read signal with respect to the conversion clock. This can be
seen in Figure 26 and with the timing specifications. A more detailed description of the timing is given in the section
timing and signal description of the THS1209.
Sample N
Channel 1, 2
Sample N+1
Channel 1, 2
Sample N+2
Channel 1, 2
Sample N+3
Channel 1, 2
Data N–1
Channel 2
Data N
Channel 1
Data N
Channel 2
Data N+1
Channel 1
Data N–2
Channel 1
Data N–2
Channel 2
Data N–1
Channel 1
AIN
CONV_CLK
READ
READ is the logical combination from CS0, CS1 and RD
SYNC
td(A)
td(pipe)
tw(CONV_CLKH)
tw(CONV_CLKL)
tc
tsu(CONV_CLKL-READL)
tsu(READH-CONV_CLKL)
td(CONV_CLKL-SYNCL)
td(CONV_CLKL-SYNCH)
Figure 26. Conversion Timing in 2 Channel Operation
相關(guān)PDF資料
PDF描述
THS1209IDA 2-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32
THS1209CDA 2-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32
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