參數(shù)資料
型號(hào)： THS1230IPW
廠商： Texas Instruments
文件頁(yè)數(shù)： 6/25頁(yè)
文件大?。?/td> 0K
描述： IC 12 BIT 30 MSPS A/D 28-TSSOP
產(chǎn)品培訓(xùn)模塊： Data Converter Basics
標(biāo)準(zhǔn)包裝： 50
位數(shù)： 12
采樣率（每秒）： 30M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 220mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 28-TSSOP
包裝： 管件
輸入數(shù)目和類型： 1 個(gè)差分，單極
產(chǎn)品目錄頁(yè)面： 895 (CN2011-ZH PDF)
配用： 296-10012-ND - EVALUATION MODULE FOR THS1230
其它名稱： 296-2838-5
www.ti.com
VIN+
VIN
R1
R2
+
R1
R2
+
C1
C2
THS1230
AIN+
AIN
REFT
REFB
AVDD
2
THS1230
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
The analog input of the THS1230 is a differential input that can be configured in various ways depending on the
signal source and the required level of performance. A fully differential connection (see Figure 17) delivers the
best performance from the converter.
Figure 17. AC-Coupled Differential Input
The analog input can be dc-coupled (see Figure 18) as long as the inputs are within the analog input common
mode voltage range. For example (see Figure 18), V+ and V– are signals centered on GND with a peak-to-peak
voltage of 2 V, and the circuit in Figure 18 is used to interface it with the THS1230. Assume AVDD of the
converter is 3 V. Two problems have to be solved. The first is to shift common mode level (CML) from 0 V to 1.5
V (AVDD/2). To do that, a V bias voltage and an adequate ratio of R1 and R2 have to be selected. For instance, if
V bias = AVDD = 3 V, then R1 = R2. The second is that the differential voltage has to be reduced from 4 V (2 x 2
V) to 1 V, and for that an attenuation of 4 to1 is needed. The attenuation is determined by the relation:
(R3||2R2)/((R3||2R2) + 2R1). One possible solution is R1 = R2 = R3 = 150
. In this case, moreover, the input
impedance (2R1 + (R3||2R2)) will be 400
. The values can be changed to match any other input impedance. A
capacitor, C, connected from AIN+ to AIN– helps filter any high frequency noise on the inputs, also improving
performance. Note that the chosen value of capacitor C must take into account the highest frequency component
of the analog input signal.
14
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