參數(shù)資料
型號(hào)： THS1240CPHP
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 1-CH 12-BIT DELTA-SIGMA ADC, PARALLEL ACCESS, PQFP48
封裝： POWER, PLASTIC, TQFP-48
文件頁(yè)數(shù)： 12/20頁(yè)
文件大?。?/td> 450K
代理商： THS1240CPHP
THS1240
12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS279D – JUNE 2000 – REVISED JANUARY 2001
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
functional block diagram
Digital Error Correction
S/H
Stage 1
Stage 10
Reference
3.0 V
2.0 V
AVDD/2
Timing
VIN–
VREFOUT+
VCM
CLK+
DVSS
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
AVDD DVDD
D/A
Σ
A/D
Σ
D/A
A/D
VREFOUT–
VREFIN+
VREFIN–
CLK–
1
2
1
Buffer
DRVDD
AVSS
DRVSS
Stages 2 – 9
VIN+
Stage 11
D10
D11
1 k
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
AVDD
2, 5, 12, 43,
45, 47
I
Analog power supply
AVSS
1, 11, 13, 41,
42, 44, 46
I
Analog ground return for internal analog circuitry
CLK+
15
I
Clock input
CLK–
16
I
Complementary clock input
D11–D0
25–36
O
Digital data output bits; LSB= D0, MSB = D11 (2s complement output format)
DRVDD
24, 37, 38
I
Digital output driver supply
DRVSS
23, 39, 40
I
Digital output driver ground return
DVDD
17, 20, 22
I
Positive digital supply
DVSS
18, 19, 21
I
Digital ground return
VBG
10
O
Band gap reference. Bypass to ground with a 1-
F and a 0.01-F chip capacitor.
VCM
48
O
Common mode voltage output. Bypass to ground with a 0.1-
F and a 0.01-F chip capacitor.
VIN+
3
I
Analog signal input
VIN–
4
I
Complementary analog signal input
VREFIN –
7
I
External reference input low
VREFIN+
8
I
External reference input high
VREFOUT+
9
O
Internal reference output. Compensate with a 1-
F and a 0.01-F chip capacitor.
VREFOUT –
6
O
Internal reference output. Compensate with a 1-
F and a 0.01-F chip capacitor.
相關(guān)PDF資料
PDF描述
THS1240I 1-CH 12-BIT DELTA-SIGMA ADC, PARALLEL ACCESS, PQFP48
THS1240C 1-CH 12-BIT DELTA-SIGMA ADC, PARALLEL ACCESS, PQFP48
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