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參數(shù)資料
| 型號： | THS1401IPFBG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | GREEN, PLASTIC, TQFP-48 |
| 文件頁數(shù)： | 7/28頁 |
| 文件大小： | 625K |
| 代理商： | THS1401IPFBG4 |
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THS1401
THS1403
THS1408
SLAS248D DECEMBER 1999 REVISED SEPTEMBER 2005
www.ti.com
15
PRINCIPLES OF OPERATION
registers
The device contains several registers. The A register is selected by the values of bits A1 and A0:
A1
A0
Register
0
Conversion result
0
1
PGA
1
0
Offset
1
Control
Tables 1 and 2 describe how to read the conversion results and how to configure the data converter. The default
values (were applicable) show the state after a power-on reset.
Table 1. Conversion Result Register, Address 0, Read
BIT
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Function
MSB
...
…
LSB
The output can be configured for 2s complement or straight binary format (see D11/control register).
The output code is given by:
2s complement:
Straight binary:
8192 at
IN = REF
0
at
IN = REF
0
at
IN = 0
8192
at
IN = 0
8191
IN = +REF 1 LSB
16383 at
IN = + REF 1 LSB
1LSB
+ 2DREF
16384
Table 2. PGA Gain Register, Address 1, Read/Write
BIT
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Function
X
G2
G1
G0
Default
0
The PGA gain is determined by writing to G20.
Gain (dB) = 1dB
× G20. max = 7dB. The range of G20 is 0 to 7.
Table 3. Offset Register, Address 2, Read/Write
BIT
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Function
X
MSB
…
LSB
Default
0
The offset correction range is from –128 to 127 LSB. This value is added to the conversion results from the ADC.
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