參數(shù)資料
型號: THS1403EVM
廠商: Texas Instruments, Inc.
英文描述: THS1403EVM(THS1403評估板)
中文描述: THS1403EVM(THS1403評估板)
文件頁數(shù): 28/39頁
文件大小: 523K
代理商: THS1403EVM
THS14xx Software Example for C6x0x DSPs
3-11
Circuit Description
3.3
THS14xx Software Example for C6x0x DSPs
The THS14xx example is available for C6x0x DSPs. It supports a single
THS1408, THS1403, THS1401, THS14F03 or THS14F01. It is written in C.
The THS14xx must be connected to the external memory interface of the DSP.
The addresses can be specified for all the four registers of the THS14xx by
changing the following #define values in the source code:
#define ADC_RES_ADDR (unsigned int *) (0x01400040)
#define ADC_PGA_ADDR (unsigned int *) (0x01400044)
#define ADC_OFF_ADDR (unsigned int *) (0x01400048)
#define ADC_CTL_ADDR (unsigned int *) (0x0140004C)
The example supports both FIFO and FIFO-less operation. It uses one DMA
channel (DMA0) and one interrupt (DMA_Channel_0). The interrupt service
routine must be included in the interrupt dispatch mechanism by the user. It
is recommended to use DSP/BIOS (default).
3.3.1
Constraints
Only one THS14xx is supported because of system performance limita-
tions and limited DSP resources.
For FIFO operation, the INT pin of the THS14F0x must be connected to
EXT_INT7. This input is used to synchronize the DMA with the interrupt
signal from the ADC. The EVM maps the INT signal to the EXT_INT7 input
of the DSP, if the C6201 EVM from TI is used.
For non-FIFO operation the master clock signal of the THS140x must be
connected to EXT_INT7. If the DSP timer output is used, the user must
modify the
DMA_CTRL_VALUE
field to synchronize the DMA with the timer.
3.3.2
Device Selection
void ths140x_configure(unsigned int pga, unsigned int off-
set, unsigned int ctrl);
The example requires that the onboard oscillator of the EVM is used as a sam-
ple clock. Therefore, the example is independent on the speed grade used
(THS1408, THS1403, THS1401 or THS14F03, THS14F01). FIFO or non-
FIFO operation is determined by the control value (FC, bit #4 of the control reg-
ister). The control value is defined by:
#define
/*
/*
/*
/*
/*
/*
ADC_CTRL (0x08F8)
8
F
2‘s complement output */
OFF = 1, offset correction enabled */
IP = 1, INT high active */
FP = 1, FIFO OVL high active */
FC = 1, FIFO enabled */
F3:0 = 8, 16 word trigger level */
8
In this example, the FIFO is enabled.
3.3.3
Configuration
void ths140x_configure(unsigned int pga, unsigned int
offset, unsigned int ctrl);
This function initializes the ADC (PGA, offset register , control register).
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