參數(shù)資料
型號: THS4211EVM
廠商: Texas Instruments, Inc.
英文描述: THS4211 Evalutation Module(THS4211評估板)
中文描述: THS4211 Evalutation模塊(THS4211評估板)
文件頁數(shù): 8/14頁
文件大小: 364K
代理商: THS4211EVM
1-1
Introduction and Description
Introduction and Description
This EVM provides a platform for testing the THS4211 in 8-pin LLP (DRB)
package in a noninverting, unity gain mode. It contains the high-speed op amp,
a number of passive components, and various features and footprints that
enable the user to experiment, test, and verify various operational amplifier
circuit implementations.
The THS4211 unity gain EVM was developed to reduce peaking caused by
lead inductance in the feedback path, which proved to be excessive in a more
general layout. This EVM is designed to minimize peaking in the unity gain
configuration. Each pad and trace on a PCB has an associated inductance,
which, in conjunction with the inductance associated with the package, may
cause peaking in the frequency response, hence, cause the device to become
unstable.
Minimizing the inductance in the feedback path is critical for reducing the peak-
ing of the frequency response in unity gain. The recommended maximum in-
ductance allowed in the feedback path is 4 nH. This can be calculated by using
the following equation:
L(nH)
K
ln
2
W
T
0.223W
T
0.5
where
W = Width of trace
Length of the trace
T = Thickness of the trace
K = 5.08 nH/inch
K = 0.2 nH/mm for Getek 4.2 epoxy polyphenylene oxide resin.
Dimensions are in inches unless otherwise specified.
Chapter 1
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