參數(shù)資料
型號(hào): THS4502CDGNT
廠(chǎng)商: Texas Instruments, Inc.
元件分類(lèi): 運(yùn)動(dòng)控制電子
英文描述: WIDEBAND, LOW-DISTORTION FULLY DIFFERENTIAL AMPLIFIERS
中文描述: 寬帶,低失真全差動(dòng)放大器
文件頁(yè)數(shù): 30/40頁(yè)
文件大?。?/td> 609K
代理商: THS4502CDGNT
THS4502
THS4503
SLOS352D
APRIL 2002
REVISED JANUARY 2004
www.ti.com
30
2.
Place five holes in the area of the thermal pad. These
holes should be 13 mils in diameter. Keep them small
so that solder wicking through the holes is not a
problem during reflow.
3.
Additional vias may be placed anywhere along the
thermal plane outside of the thermal pad area. This
helps dissipate the heat generated by the THS4500
family IC. These additional vias may be larger than the
13-mil diameter vias directly under the thermal pad.
They can be larger because they are not in the thermal
pad area to be soldered so that wicking is not a
problem.
4.
Connect all holes to the internal ground plane.
5.
When connecting these holes to the ground plane,
do
not
use the typical web or spoke via connection
methodology. Web connections have a high thermal
resistance connection that is useful for slowing the
heat transfer during soldering operations. This makes
the soldering of vias that have plane connections
easier. In this application, however, low thermal
resistance is desired for the most efficient heat
transfer. Therefore, the holes under the THS4500
family PowerPAD package should make their
connection to the internal ground plane with a
complete connection around the entire circumference
of the plated-through hole.
6.
The top-side solder mask should leave the terminals
of the package and the thermal pad area with its five
holes exposed. The bottom-side solder mask should
cover the five holes of the thermal pad area. This
prevents solder from being pulled away from the
thermal pad area during the reflow process.
7.
Apply solder paste to the exposed thermal pad area
and all of the IC terminals.
8.
With these preparatory steps in place, the IC is simply
placed in position and run through the solder reflow
operation
as
any
standard
component. This results in a part that is properly
installed.
surface-mount
POWER DISSIPATION AND THERMAL
CONSIDERATIONS
The THS4500 family of devices does not incorporate
automatic thermal shutoff protection, so the designer must
take care to ensure that the design does not violate the
absolute maximum junction temperature of the device.
Failure may result if the absolute maximum junction
temperature of 150
°
C is exceeded. For best performance,
design for a maximum junction temperature of 125
°
C.
Between 125
°
C and 150
°
C, damage does not occur, but
the performance of the amplifier begins to degrade.
The thermal characteristics of the device are dictated by
the package and the PC board. Maximum power
dissipation for a given package can be calculated using the
following formula.
P
Dmax
T
max
T
A
JA
Where:
P
Dmax
is the maximum power dissipation in the amplifier (W).
T
max
is the absolute maximum junction temperature (
°
C)
.
T
A
is the ambient temperature (
°
C).
θ
JA
=
θ
JC
+
θ
CA
θ
JC
is the thermal coefficient from the silicon junctions to the
case (
°
C/W).
θ
CA
is the thermal coefficient from the case to ambient air
(
°
C/W).
(28)
For systems where heat dissipation is more critical, the
THS4500 family of devices is offered in an 8-pin MSOP
with PowerPAD. The thermal coefficient for the MSOP
PowerPAD package is substantially improved over the
traditional SOIC. Maximum power dissipation levels are
depicted in the graph for the two packages. The data for
the DGN package assumes a board layout that follows the
PowerPAD layout guidelines referenced above and
detailed in the PowerPAD application notes in the
Additional Reference Material
section at the end of the
data sheet.
2
1.5
1
0
40
20
T
A
Ambient Temperature
°
C
θ
JA
= 170
°
C/W for 8-Pin SOIC (D)
θ
JA
= 58.4
°
C/W for 8-Pin MSOP (DGN)
Τ
J
= 150
°
C, No Airflow
Figure 113. Maximum Power Dissipation vs
Ambient Temperature
0
20
P
2.5
3
3.5
40
60
80
8-Pin DGN Package
0.5
8-Pin D Package
When determining whether or not the device satisfies the
maximum power dissipation requirement, it is important to
not only consider quiescent power dissipation, but also
dynamic power dissipation. Often times, this is difficult to
quantify because the signal pattern is inconsistent, but an
estimate of the RMS power dissipation can provide
visibility into a possible problem.
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