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參數(shù)資料
| 型號(hào)： | THS5641AIDWG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | PARALLEL, 8 BITS INPUT LOADING, 0.035 us SETTLING TIME, 8-BIT DAC, PDSO28 |
| 封裝： | GREEN, PLASTIC, SOIC-28 |
| 文件頁數(shù)： | 5/31頁 |
| 文件大?。?/td> | 915K |
| 代理商： | THS5641AIDWG4 |
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THS5641A
8BIT, 100 MSPS, CommsDAC
DIGITALTOANALOG CONVERTER
SLAS277A MARCH 2000 REVISED SEPTEMBER 2002
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
The THS5641A architecture is based on current steering, combining high update rates with low power
consumption. The CMOS device consists of a segmented array of PMOS transistor current sources, which are
capable of delivering a full-scale current up to 20 mA. High-speed differential current switches direct the current
of each current source to either one of the output nodes, IOUT1 or IOUT2. The complementary output currents
thus enable differential operation, canceling out common mode noise sources (on-chip and PCB noise), dc
offsets, even order distortion components, and increase signal output power by a factor of two. Major
advantages of the segmented architecture are minimum glitch energy, excellent DNL, and very good dynamic
performance. The DAC’s high output impedance of >300 k
and fast switching result in excellent dynamic
linearity (spurious free dynamic range SFDR).
The full-scale output current is set using an external resistor RBIAS in combination with an on-chip bandgap
voltage reference source (1.2 V) and control amplifier. The current IBIAS through resistor RBIAS is mirrored
internally to provide a full-scale output current equal to 32 times IBIAS. The full-scale current can be adjusted
from 20 mA down to 2 mA.
data interface and timing
The THS5641A comprises separate analog and digital supplies, i.e. AVDD and DVDD. The analog and digital
supply voltage can be set independently from 5.5 V down to 3 V. The THS5641A provides two operating modes,
as shown in Table 1. Mode 0 (mode pin connected to DGND) supports a straight binary input data word format,
whereas mode 1 (mode pin connected to DVDD) sets a twos complement input configuration.
Figure 23 shows the timing diagram. Internal edge-triggered flip-flops latch the input word on the rising edge
of the input clock. The THS5641A provides for minimum setup and hold times (> 1 ns), allowing for noncritical
external interface timing. Conversion latency is one clock cycle for both modes. The clock duty cycle can be
chosen arbitrarily under the timing constraints listed in the digital specifications table. However, a 50% duty cycle
will give optimum dynamic performance. Figure 24 shows a schematic of the equivalent digital inputs of the
THS5641A, valid for pins D7D0, SLEEP, and CLK. The digital inputs are CMOS-compatible with logic
thresholds of DVDD/2 ±20%. Since the THS5641A is capable of being updated up to 100 MSPS, the quality of
the clock and data input signals are important in achieving the optimum performance. The drivers of the digital
data interface circuitry should be specified to meet the minimum setup and hold times of the THS5641A, as well
as its required min/max input logic level thresholds. Typically, the selection of the slowest logic family that
satisfies the above conditions will result in the lowest data feed-through and noise. Additionally, operating the
THS5641A with reduced logic swings and a corresponding digital supply (DVDD) will reduce data feed-through.
Note that the update rate is limited to 67 MSPS for a digital supply voltage DVDD of 3 V to 3.6 V.
相關(guān)PDF資料 |
PDF描述 |
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| THS5641AIPWRG4 | PARALLEL, 8 BITS INPUT LOADING, 0.035 us SETTLING TIME, 8-BIT DAC, PDSO28 |
| THS5641AIDWR | PARALLEL, 8 BITS INPUT LOADING, 0.035 us SETTLING TIME, 8-BIT DAC, PDSO28 |
| THS5641IDWR | PARALLEL, 8 BITS INPUT LOADING, 0.035 us SETTLING TIME, 8-BIT DAC, PDSO28 |
| THS5641IDW | PARALLEL, 8 BITS INPUT LOADING, 0.035 us SETTLING TIME, 8-BIT DAC, PDSO28 |
| THS5641IPW | PARALLEL, 8 BITS INPUT LOADING, 0.035 us SETTLING TIME, 8-BIT DAC, PDSO28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| THS5641AIDWR | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 8-Bit 100 MSPS CommsDAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| THS5641AIDWRG4 | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 8-Bit 100 MSPS CommsDAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| THS5641AIPW | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 8-Bit 100 MSPS CommsDAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| THS5641AIPWG4 | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 8-Bit 100 MSPS CommsDAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| THS5641AIPWR | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 8-Bit 100 MSPS CommsDAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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