參數(shù)資料
型號: THS5671APW
廠商: Texas Instruments, Inc.
英文描述: 14-BIT, 125 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER
中文描述: 14位,125 MSPS的,CommsDAC數(shù)字模擬轉(zhuǎn)換器
文件頁數(shù): 4/31頁
文件大?。?/td> 825K
代理商: THS5671APW
THS5671A
14-BIT 125 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS201A
DECEMBER 1999
REVISED SEPTEMBER 2002
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, AV
DD
= 5 V,
DV
DD
= 5 V, IOUT
FS
= 20 mA (unless otherwise noted)
dc specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
DC accuracy
INL
14
Bits
Integral nonlinearity
TA= 40
TA =
°
C to 85
°
C
7
±
2.5
±
2
7
LSB
DNL
Differential nonlinearity
3.5
3.5
LSB
Monotonicity
At 11-bit level
Monotonic
Analog output
Offset error
0.02
%FSR
Gain error
Without internal reference
2.3
%FSR
With internal reference
1.3
Full scale output current
2
20
mA
Output compliance range
AVDD = 5 V, IOUTFS = 20 mA
1
1.25
V
k
pF
Output resistance
300
Output capacitance
5
Reference output
Reference voltage
Reference output current
§
1.18
1.22
1.32
V
100
nA
Reference input
VEXTIO
Input voltage range
0.1
1.25
V
Input resistance
Small signal bandwidth
1
M
MHz
Without CCOMP1
1.3
Input capacitance
100
pF
Temperature coefficients
Offset drift
0
Gain drift
Without internal reference
±
40
±
120
±
35
ppm of
FSR/
°
C
With internal reference
Reference voltage drift
Power supply
AVDD
DVDD
Analog supply voltage
4.5
5
5.5
V
Digital supply voltage
3
5.5
V
IAVDD
Analog supply current
25
30
mA
Sleep mode supply current
Digital supply current#
Sleep mode
3
5
mA
IDVDD
5
6
mA
Power dissipation
||
AVDD = 5 V, DVDD = 5 V, IOUTFS = 20 mA
175
±
0.4
mW
AVDD
DVDD
Power supply rejection ratio
%FSR/V
±
0.025
Operating range
40
85
°
C
Measured at IOUT1 in virtual ground configuration.
Nominal full-scale current IOUTFS equals 32X the IBIAS current.
§
Use an external buffer amplifier with high impedance input to drive any external load.
Reference bandwidth is a function of external cap at COMP1 pin and signal level.
#Measured at fCLK = 50 MSPS and fOUT= 1 MHz.
||Measured for 50
RLOAD at IOUT1 and IOUT2, fCLK = 50 MSPS and fOUT = 20 MHz.
Specifications subject to change
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