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THS7001, THS7002
70-MHz PROGRAMMABLE-GAIN AMPLIFIERS
SLOS214B – OCTOBER 1998 – REVISED AUGUST 1999
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
preamp operating characteristics, G = 2, T
A
= 25
°
C, R
L
= 150
, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SR
Slew rate (see Note 4)
G = 1
G = –1
VO =
±
2 V,
VCC =
±
5 V
VO =
±
10 V,
VCC =
±
15 V
VCC =
±
5 V
VCC =
±
15 V
VCC =
±
5 V
VCC =
±
15 V
fc = 1 MHz,
RL = 250
f = 10 kHz
65
V/
μ
s
85
Settling time to 0 1%
Settling time to 0.1%
85
ts
G = –1,
5 V Step
70
ns
Settling time to 0 01%
Settling time to 0.01%
95
90
THD
Total harmonic distortion
VCC =
±
15 V,
VO(PP) = 2V
VCC =
±
5 V or
±
15 V,
VCC =
±
5 V or
±
15 V,
VO(PP) = 0.4V,
G = 2
–88
dBc
Vn
In
Input noise voltage
1.7
nV/
√
Hz
pA/
√
Hz
Input noise current
f = 10 kHz
VCC =
±
5 V
VCC =
±
15 V
VCC =
±
5 V
VCC =
±
15 V
VO = 5 VO(PP)
VO = 20 VO(PP)
VCC =
±
5 V
VCC =
±
15 V
VCC =
±
5 V
VCC =
±
15 V
TA = 25
°
C
0.9
BW
Small signal bandwidth ( 3 dB)
Small-signal bandwidth (–3 dB)
85
MHz
100
Bandwidth for 0 1 dB flatness
Bandwidth for 0.1 dB flatness
VO(PP) = 0.4V,
G = 2
35
MHz
45
Full power bandwidth (see Note 5)
VCC =
±
5 V
,
VCC =
±
15 V
,
4.1
MHz
1.4
AD
Differential gain error
G = 2, 100 IRE,
G 2, 100 IRE,
NTSC
0.02%
0.02%
0.01
°
0.01
°
φ
D
Differential phase error
G = 2, 100 IRE,
G 2, 100 IRE,
NTSC
VCC =
±
5 V,
2 5 V
VO =
±
2.5 V,
RL = 1 k
VCC =
±
15 V,
VO =
±
10 V, RL = 1 k
VCC =
±
5 V or
±
15 V,
85
89
Open loop gain
O en loo gain
TA = full range
TA = 25
°
C
TA = full range
f = 1 MHz
83
dB
86
91
84
Channel-to-channel crosstalk (THS7002)
Full range for the THS7001/02C is 0
°
C to 70
°
C. Full range for the THS7001/02I is –40
°
C to 85
°
C.
NOTES:
4. Slew rate is measured from an output level range of 25% to 75%.
5. Full power bandwidth = slew rate/2
π
V(PP).
–85
dB
shutdown electrical characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
0.2
MAX
0.3
UNIT
Standby current, disabled
(per channel)
( er channel)
t di
bl d
Preamp
VCC =
±
5 V
VCC =
±
15 V
VCC =
±
5 V or
±
15 V
ICC(standby)
VI(SHDN) = 2.5 V
0.65
0.8
mA
PGA
0.8
1.2
VIH(SHDN)
VIL(SHDN)
IIH(SHDN)
IIL(SHDN)
tdis
ten
Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the supply current
has reached half its final value.
Shutdown voltage for power up
VCC=
±
±
VCC =
5 V or
15 V,
Relative to GND
0.8
V
Shutdown voltage for power down
2
V
Shutdown input current high
VCC=
±
±
VCC =
5 V or
15 V,
VI(SHDN) = 5 V
VI(SHDN) = 0.5 V
Preamp and PGA
300
400
μ
A
μ
A
Shutdown input current low
Disable time
Enable time
25
50
VCC =
±
5 V or
±
15 V,
VCC =
±
5 V or
±
15 V,
100
ns
μ
s
Preamp and PGA
1.5