參數(shù)資料
型號: THS7364IPW
廠商: TEXAS INSTRUMENTS INC
元件分類: 音頻/視頻放大
英文描述: 6 CHANNEL, VIDEO AMPLIFIER, PDSO20
封裝: GREEN, PLASTIC, TSSOP-20
文件頁數(shù): 32/47頁
文件大?。?/td> 1134K
代理商: THS7364IPW
SBOS530 – AUGUST 2010
www.ti.com
EVALUATION MODULE
To evaluate the THS7364, an evaluation module
The
EVM
default
output
configuration
sets
all
(EVM) is available. The THS7364EVM allows for
channels for ac output coupling. The 470-mF and
testing the THS7364 in many different configurations.
0.1-mF capacitors work well for most ac-coupled
Inputs and outputs include BNC connectors and RCA
systems. However, if dc-coupled output is desired,
connectors commonly found in video systems, along
then replacing the 0.1-mF capacitors (C20, C22, C24,
with 75-
input termination resistors, 75- series
C26, C28, and/or C30) with 0-
resistors works well.
source termination resistors, and 75-
characteristic
Removing the 470-mF capacitors is optional, but
impedance traces. Several unpopulated component
removing them from the EVM eliminates a few
pads are found on the EVM to allow for different input
picofarads of stray capacitance on each signal path
and output configurations as dictated by the user.
which may be desirable.
This EVM is designed to be used with a single supply
The THS7364 incorporates an easy method to
from 2.6 V up to 5 V.
configure the bypass modes and the disable modes.
The EVM default input configuration sets all channels
The use of JP4 controls the SD channels disable
for dc input coupling. The input signal must be within
feature; JP6 controls the FHD channels disable
0 V to approximately 1.4 V for proper operation.
feature; JP3 controls the SD channels filter/bypass
Failure to be within this range saturates and/or clips
mode;
and
JP5
controls
the
FHD
channels
the output signal. If the input range is beyond this, if
filter/bypass mode.
the signal voltage is unknown, or if coming from a
Connection of JP4 and JP6 to GND applies 0 V to the
current sink DAC, then ac input configuration is
disable pins and the THS7364 operates normally.
desired. This option is easily accomplished with the
Moving JP4 to +VS causes the THS7364 SD
EVM by simply replacing the Z1 through Z6 0-
channels to be in disable mode, while moving JP6 to
resistors with 0.1-mF capacitors.
+VS causes the THS7364 FHD channels to be in
For an ac-coupled input and sync-tip clamp (STC)
disable mode.
functionality commonly used for CVBS, s-video Y',
Connection of JP3 to GND places the THS7364 SD
component Y' signals, and R'G'B' signals, no other
channels in filter mode while moving JP3 to +VS
changes are needed. However, if a bias voltage is
places the THS7364 SD channels in bypass mode.
needed after the input capacitor which is commonly
Connection of JP5 to GND places the THS7364 FHD
needed for s-video C', component P'B, and P'R, then a
channels in filter mode while moving JP5 to +VS
pull-up resistor should be added to the signal on the
places the THS7364 FHD channels in bypass mode.
EVM. This configuration is easily achieved by simply
adding a resistor to any of the following resistor pads;
83 shows
the
THS7364EVM
schematic.
RX7 to RX12. A common value to use is 3.3 M
.
Figure 84 and Figure 85 illustrate the two layers of
Note that even signals with embedded sync can also
the EVM PCB, incorporating standard high-speed
use bias mode if desired.
layout practices. Table 5 lists the bill of materials as
the board comes supplied from Texas Instruments.
38
Copyright 2010, Texas Instruments Incorporated
Product Folder Link(s): THS7364
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