參數(shù)資料
型號: THS7365IPW
廠商: TEXAS INSTRUMENTS INC
元件分類: 音頻/視頻放大
英文描述: 6 CHANNEL, VIDEO AMPLIFIER, PDSO20
封裝: PLASTIC, TSSOP-20
文件頁數(shù): 38/52頁
文件大?。?/td> 1599K
代理商: THS7365IPW
EVALUATION MODULE
www.ti.com.................................................................................................................................................................................................. SBOS467 – MARCH 2009
To evaluate the THS7365, an evaluation module
The
EVM
default
output
configuration
sets
all
(EVM) is available. The EVM allows for testing the
channels for ac output coupling. The 470-
F and
THS7365 in many different configurations. Inputs and
0.1-
F capacitors work well for most ac-coupled
outputs include BNC connectors commonly found in
systems. However, if dc-coupled output is desired,
video systems, along with 75-
input termination
then replacing the 0.1-
F capacitors (C20, C22, C24,
resistors, 75-
series source termination resistors,
C26, C28, and/or C30) with 0-
resistors works well.
and 75-
characteristic impedance traces. Several
Removing the 470-
F capacitors is optional, but
unpopulated component pads are found on the EVM
removing them from the EVM eliminates a few
to allow for different input and output configurations
picofarads of stray capacitance on each signal path
as dictated by the user. This EVM is designed to be
which may be desirable.
used with a single supply from 2.6 V up to 5 V.
The THS7365 incorporates an easy method to
The EVM default input configuration sets all channels
configure the bypass modes and the disable modes.
for dc input coupling. The input signal must be within
The use of JP4 controls the SD channels disable
0 V to approximately 1.4 V for proper operation.
feature; JP6 controls the HD Channels disable
Failure to be within this range saturates and/or clips
feature; JP3 controls the SD channels filter/bypass
the output signal. If the input range is beyond this, or
mode; and JP5 controls the HD channels filter/bypass
if the signal voltage is unknown, or coming from a
mode. While there is a space on the EVM for JP1
current sink DAC, then ac input configuration is
and JP2, these are not used for the THS7365.
desired. This option is easily accomplished with the
Connection of JP4 and JP6 to GND applies 0 V to the
EVM by simply replacing Z1 through Z6 0- resistors
disable pins and the THS7365 operates normally.
with 0.1-
F capacitors.
Moving JP4 to +VS causes the THS7365 SD
For ac-coupled input and sync-tip clamp (STC)
channels to be in disable mode, while moving JP6 to
functionality commonly used for CVBS, s-video Y',
+VS causes the THS7365 HD channels to be in
component Y' signals, and R'G'B' signals with
disable mode .
embedded sync, no other changes are needed.
Connection of JP3 to GND places the THS7365 SD
However, if a bias voltage is needed after the input
channels in filter mode while moving JP3 to +VS
capacitor which is commonly needed for s-video C',
places the THS7365 HD channels in bypass mode.
component P'B and P'R, and non-sync embedded
Connection of JP5 to GND places the THS7365 HD
R'G'B' signals, then a pull-up resistor should be
channels in filter mode while moving JP5 to +VS
added to the signal on the EVM. This configuration is
places the THS7365 HD channels in bypass mode.
easily achieved by simply adding a resistor to any of
the following resistor pads; RX7 to RX12. A common
Figure 122 shows the EVM schematic. Figure 123
value to use is 3.3 M
. Note that even signals with
and Figure 124 illustrate the two layers of the EVM
embedded sync can also use bias mode if desired.
PCB,
incorporating
standard
high-speed
layout
practices. Table 1 lists the bill of materials as the
board comes supplied from Texas Instruments.
Copyright 2009, Texas Instruments Incorporated
43
Product Folder Link(s): THS7365
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