www.ti.com
SBOS497 – DECEMBER 2009
EVALUATION MODULE
C26, C28, and/or C30) with 0-
resistors works well.
To evaluate the THS7368, an evaluation module
Removing the 470-
μF capacitors is optional, but
(EVM) is available. The THS7368EVM allows for
removing them from the EVM eliminates a few
testing the THS7368 in many different configurations.
picofarads of stray capacitance on each signal path
Inputs and outputs include BNC connectors and RCA
which may be desirable.
connectors commonly found in video systems, along
with 75-
input termination resistors, 75- series
The THS7368 incorporates an easy method to
source termination resistors, and 75-
characteristic
configure the bypass modes and the disable modes.
impedance traces. Several unpopulated component
The use of JP4 controls the SD channels disable
pads are found on the EVM to allow for different input
feature; JP6 controls the SF channels disable feature;
and output configurations as dictated by the user.
JP3 controls the SD channels filter/bypass mode; and
This EVM is designed to be used with a single supply
JP5 controls the SF channels filter/bypass mode.
from 2.6 V up to 5 V.
Note that the EVM silkscreen shows HD rather than
SF.
The EVM default input configuration sets all channels
for dc input coupling. The input signal must be within
Connection of JP4 and JP6 to GND applies 0 V to the
0 V to approximately 1.4 V for proper operation.
disable pins and the THS7368 operates normally.
Failure to be within this range saturates and/or clips
Moving JP4 to +VS causes the THS7368 SD
the output signal. If the input range is beyond this, if
channels to be in disable mode, while moving JP6 to
the signal voltage is unknown, or if coming from a
+VS causes the THS7368 SF channels to be in
current sink DAC, then ac input configuration is
disable mode.
desired. This option is easily accomplished with the
Connection of JP3 to GND places the THS7368 SD
EVM by simply replacing the Z1 through Z6 0-
channels in filter mode while moving JP3 to +VS
resistors with 0.1-
μF capacitors.
places the THS7368 SD channels in bypass mode.
For an ac-coupled input and sync-tip clamp (STC)
Connection of JP5 to GND places the THS7368 SF
functionality commonly used for CVBS, s-video Y',
channels in filter mode while moving JP5 to +VS
component Y' signals, and R'G'B' signals, no other
places the THS7368 SF channels in bypass mode.
changes are needed. However, if a bias voltage is
The filter selection is also easily accomplished by
needed after the input capacitor which is commonly
using jumpers JP1 and JP2. JP1 controls the logic
needed for s-video C', component P'B, and P'R, then a
voltage for the filter 1 pin while JP2 controls the logic
pull-up resistor should be added to the signal on the
EVM. This configuration is easily achieved by simply
the truth table for the filter selection and the
adding a resistor to any of the following resistor pads;
appropriate logic. The EVM also has a truth table
RX7 to RX12. A common value to use is 3.3 M
.
printed on it for easy reference.
Note that even signals with embedded sync can also
use bias mode if desired.
the
THS7368EVM
schematic.
The
EVM
default
output
configuration
sets
all
the EVM PCB, incorporating standard high-speed
channels for ac output coupling. The 470-
μF and
layout practices.
Table 7 lists the bill of materials as
0.1-
μF capacitors work well for most ac-coupled
the board comes supplied from Texas Instruments.
systems. However, if dc-coupled output is desired,
then replacing the 0.1-
μF capacitors (C20, C22, C24,
Copyright 2009, Texas Instruments Incorporated
31