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| 型號： | THS7368IPWR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 6 CHANNEL, VIDEO AMPLIFIER, PDSO20 |
| 封裝： | GREEN, TSSOP-20 |
| 文件頁數(shù)： | 37/40頁 |
| 文件大?。?/td> | 1123K |
| 代理商： | THS7368IPWR |
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SBOS497 – DECEMBER 2009
www.ti.com
ELECTRICAL CHARACTERISTICS: VS+ = +3.3 V (continued)
At TA = +25°C, RL = 150 to GND, Filter mode, and dc-coupled input/output, unless otherwise noted.
THS7368
TEST
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
LEVEL(1)
DC PERFORMANCE
VIN = 0 V, SD channels
200
305
400
mV
A
Biased output voltage
VIN = 0 V, SF channels
200
300
400
mV
A
Input voltage range
DC input, limited by output
–0.1/1.46
V
C
VIN = –0.1 V, SD channels
140
200
μA
A
Sync-tip clamp charge current
VIN = –0.1 V, SF channels
280
400
μA
A
Input impedance
800 || 2
k
|| pF
C
OUTPUT CHARACTERISTICS
RL = 150 to +1.65 V
3.15
V
C
RL = 150 to GND
2.85
3.1
V
A
High output voltage swing
RL = 75 to +1.65 V
3.1
V
C
RL = 75 to GND
3
V
C
RL = 150 to +1.65 V (VIN = –0.2 V)
0.06
V
C
RL = 150 to GND (VIN = –0.2 V)
0.05
0.12
V
A
Low output voltage swing
RL = 75 to +1.65 V (VIN = –0.2 V)
0.1
V
C
RL = 75 to GND (VIN = –0.2 V)
0.05
V
C
Output current (sourcing)
RL = 10 to +1.65 V
80
mA
C
Output current (sinking)
RL = 10 to +1.65 V
70
mA
C
POWER SUPPLY
Operating voltage
2.6
3.3
5.5
V
B
VIN = 0 V, all channels on
18.8
23.4
28.5
mA
A
VIN = 0 V, SD channels on, SF channels off
5.6
6.9
9
mA
A
Total quiescent current, no load
VIN = 0 V, SD channels off, SF channels on
13.2
16.5
19.5
mA
A
VIN = 0 V, all channels off, VDISABLE = 3 V
0.1
10
μA
A
Power-supply rejection ratio
At dc
52
dB
C
(PSRR)
LOGIC CHARACTERISTICS(6)
VIH
Disabled or Bypass engaged
1.6
1.4
V
A
VIL
Enabled or Bypass disengaged
0.75
0.6
V
A
IIH
Applied voltage = 3.3 V
1
μA
C
IIL
Applied voltage = 0 V
1
μA
C
Disable time
150
ns
C
Enable time
150
ns
C
Bypass/filter switch time
15
ns
C
(6)
The logic input pins default to a logic '0' condition when left floating.
Table 1. TRUTH TABLE: VS+ = +3.3 V
(1)
FILTER 1
FILTER 2
BYPASS SF(2)
DESCRIPTION
0
Selects the standard definition filter (9.5 MHz) for the SF channels
0
1
0
Selects the enhanced definition filter (18 MHz) for the SF channels
1
0
Selects the high definition filter (36 MHz) for the SF channels
1
0
Selects the full/true high-definition filter (72 MHz) for the SF channels
X
1
Bypasses the filters for the SF channels
(1)
The logic input pins default to a logic '0' condition when left floating.
(2)
SF indicates selectable filter.
6
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s): THS7368
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