參數(shù)資料
型號(hào)： THS8133TQFP
廠商： Texas Instruments, Inc.
英文描述： TRIPLE 10-BIT, 80 MSPS VIDEO D/A CONVERTER WITH TRI-LEVEL SYNC GENERATION
中文描述： 三路10位，80 MSPS的視頻D /與Tri轉(zhuǎn)爐電平同步發(fā)電
文件頁(yè)數(shù)： 18/23頁(yè)
文件大小： 339K
代理商： THS8133TQFP
THS8133, THS8133A, THS8133B
TRIPLE 10-BIT, 80 MSPS VIDEO D/A CONVERTER
WITH TRI-LEVEL SYNC GENERATION
SLVS204C – APRIL 1999 – REVISED SEPTEMBER 2000
18
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
SMPTE 274M (continued)
Table 9. THS8133 Signals for SMPTE 274M Compliant Operation on GBR and Y Channels
LEVEL
GBRY
SYNC
SYNC T
SYNC_T
BLANK
DAC INPUT
(mA)
(V)
White
26.67
1.000
1
X
1
3FFh
data
Video
video+8.00
video+0.3
1
X
1
Sync Pos
16.00
0.600
0
1
X
xxxh
000h
xxxh
xxxh
Black
8.00
0.3000
1
X
1
Blank
8.00
0.3000
1
X
0
Sync Neg
0
0
0
0
X
In the YPbPr mode of this standard, the sync is centered around the center span of the video amplitude levels,
as shown in Figure 14. So the current for Pb and Pr is down-shifted with respect to Y to accommodate the
minimum data level at 0 mA. Thus, an input code of 00h corresponds now to an output drive of 0 mA while the
negative sync level is at 1.33 mA, corresponding to 50 mV. The Pb and Pr data input format is offset binary.
Table 10 lists the THS8133 full-scale output currents for Pb and Pr channels in the YPbPr operation mode of
the device. The operation mode corresponds to YPbPr with sync-on-all of Table 1.
Table 10. THS8133 Signals for SMPTE 274M Compliant Operation on Pb and Pr Channels
LEVEL
Pb, Pr
SYNC
SYNC T
SYNC_T
BLANK
DAC INPUT
(mA)
(V)
Max
18.67
0.7000
1
X
1
3FFh
data
Video
video
video
1
X
1
Sync Pos
17.33
0.650
0
1
X
xxxh
xxxh
xxxh
000h
Blank
9.33
0.350
1
X
0
Sync Neg
1.33
0.050
0
0
x
Min
0
0
1
X
1
SMPTE 296M
This standard defines a raster scanning format of 1280x720 and an aspect ratio of 16:9, the analog and digital
representation, and the definition of an analog interface. Both GBR and YPbPr component color encoding can
be used.
With respect to the sync and video level definition, this standard is analogous to SMPTE 274M with the use of
a tri-level sync pulse. Therefore, for the generation of output signals compliant to this standard, refer to the
configuration of THS8133 for SMPTE 274M.
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