參數(shù)資料
型號: THS8135-240IPHP
廠商: TEXAS INSTRUMENTS INC
元件分類: DAC
英文描述: PARALLEL, WORD INPUT LOADING, 10-BIT DAC, PQFP48
封裝: POWER, TQFP-48
文件頁數(shù): 22/24頁
文件大?。?/td> 546K
代理商: THS8135-240IPHP
THS8135
TRIPLE 10-BIT, 80/240 MSPS VIDEO DAC WITH TRI-LEVEL SYNC AND VIDEO (ITU-R.BT601)
– COMPLIANT FULL SCALE RANGE
SLVSXXXX—10/02/00 3:44 PM
8
Copyright 2000 Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data
and other specifications are design goals. Texas Instruments
reserves the right to change or discontinue these products
Input data to the device can be supplied from a 3x10b GBR or YPbPr input port. If the device is configured to
take data from all three channels, the data is clocked in at each rising edge of CLK. All 3 DAC’s operate at
the full clock speed of CLK.
In the case of 4:2:2 sampled data (for YPbPr) the device can be fed over either a 2x10 bit or 1x10 bit
multiplexed input port. An internal demultiplexer will route input samples to the appropriate DAC: Y at the rate
of CLK, Pb & Pr each at rate of CLK.
According to ITU-R.BT-656 the sample sequence is Pb-Y-Pr over a 1x10 bit interface (Y-port). The sample
sequence starts at the first rising edge of CLK after /BLANK has been taken high (inactive). Note that in this
case the frequency of CLK is 2x the Y conversion speed and 4x the conversion speed of both Pr & Pb.
In the case of a 2x10 bit input interface, both the Y-port and the Pr-port are sampled on every CLK rising
edge. The Pr-port carries the sample sequence Pb-Pr. The sample sequence starts at the first rising edge of
CLK after /BLANK has been taken high (inactive). Note that in this case the frequency of CLK is equal to the
conversion speed of Y and 2x the conversion speed of both Pr & Pb.
Table 6 show the possible configurations of the input formatter, as determined by the internal M1_INT and
M2_INT signals. . The color space selection determines also the position of the blanking level, as will be
explained next.
Table 6: THS8135 RGB/YCbCr Color Space and Input Formatter Configuration
M1_INT
M2_INT
2
Configuration
Description
LL
GBR
3x10b-
4:4:4
GBR mode 4:4:4. Data clocked in on each rising edge of CLK from G, B &
R input channels.
LH
YPbPr
3x10b-
4:4:4
YpbPr mode 4:4:4. Data clocked in on each rising edge of CLK from Y,
Pb & Pr input channels.
HL
YPbPr
2x10b-
4:2:2
YPbPr mode 4:2:2 2x10 bit. Data clocked in on each rising edge of CLK
from Y channel. A sample sequence of Pb-Pr-... should be applied to the
Pr port. At the first rising edge of CLK after /BLANK is taken high, Pb
should be present on this port.
HH
YPbPr
1x10b-
4:2:2
YPbPr mode 4:2:2 1x10 bit (ITU-R.BT-656 compliant). Data clocked in on
each rising edge of CLK from Y channel. A sample sequence of Pb-Y-Pr
should be applied to the Y port. At the first rising edge of CLK after
/BLANK is taken high, Pb should be present on this port.
2 M1_INT and M2_INT are the internal logic signals set by M1 resp. M2, as explained in Tables 4 & 5.
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