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參數(shù)資料
| 型號： | THS8136PHPR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 0.015 us SETTLING TIME, 10-BIT DAC, PQFP48 |
| 封裝： | PLASTIC, TQFP-48 |
| 文件頁數(shù)： | 3/18頁 |
| 文件大?。?/td> | 377K |
| 代理商： | THS8136PHPR |
www.ti.com
SLES236A – NOVEMBER 2008 – REVISED DECEMBER 2010
ANALOG (DAC) OUTPUTS ELECTRICAL CHARACTERISTICS
over recommended operating conditions, fCLK = 180 MHz, use of internal reference voltage VREF, RFS = RFS(nom),
37.5-
load termination (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DAC resolution
10
Bits
Static, best fit, RGB with sync insertion (700 +
-1/1 –2.5/1.5
sync)
INL
Integral nonlinearity
LSB
Static, best fit, generic mode, 1.2 V output range
–1/1
Static, RGB with sync insertion (700 + sync)
–0.4/0.4
±1
DNL
Differential nonlinearity
LSB
Static, generic mode, 1.2 V output range
-0.4/0.4
Power supply ripple rejection ratio of
PSRR
f = DC(1)
38.5
dB
DAC output (full scale)
Vrefo
Voltage reference output
1.12
1.16
1.20
V
RR
VREF output resistance
284
KIMBAL
Imbalance between DACs(2)
CLK = 80 MSPS, video mode
–2
1.8
2
%
VOC
DAC output compliance voltage
0.7
1.2
V
Generic DAC mode
CLK = 80 MSPS(3)
18
18.67
19.5
IFS
mA
RGB with sync insertion enabled
CLK = 80 MSPS(3)
27
28
29.3
tRDAC
DAC output current rise time
CLK = 80 MSPS, 10 to 90% of full scale(4)
2.8
3.3
3.6
ns
tFDAC
DAC output current fall time
CLK = 80 MSPS, 10 to 90% of full scale(4)
2.8
3.3
3.6
ns
Measured from CLK = VIH(min) to 50% of
td(A)
Analog output delay
4.5
ns
full-scale transition(5)
Measured from 50% of full scale transition on
tS
Analog output settling time
15
ns
output to output settling, within 2%(4)
(1)
PSRR is measured with a 0.1-mF capacitor between the COMP and AVDD pins and with a 0.1-mF capacitor connected between the VREF
and AVSS pins. The ripple amplitude is within the range 100 mVp-p to 500 mVp-p with the DAC output set to full scale and a
double-terminated 75
(= 37.5 ) load. PSRR is defined as 20 × log(ripple voltage at DAC output/ripple voltage at AVDD input). Limits
are from characterization only.
(2)
The imbalance between DACs applies to all possible pairs of the three DACs.
(3)
Values at RFS = RFS(nom)
(4)
From characterization only. Measured on the AG channel with RFS = RFS(nom).
(5)
This value excludes the digital process delay, tD(D). Limit are from characterization only.
Copyright 2008–2010, Texas Instruments Incorporated
11
Product Folder Link(s): THS8136
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