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參數(shù)資料
| 型號： | TK5552A-PP |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Read/Write Transponder |
| 中文描述： | SPECIALTY TELECOM CIRCUIT |
| 封裝： | PLASTIC CUBE PACKAGE |
| 文件頁數(shù)： | 19/22頁 |
| 文件大小： | 326K |
| 代理商： | TK5552A-PP |
19
TK5552
4698A–RFID–04/03
Programming
When the bit decoder and controller detect a valid data stream, the transponder IC will
start an erase and programming cycle if a data write command was decoded (see Fig-
ure 23).
During the erase and programming cycle, downlink damping is turned off. The program-
ming cycle includes a data verification read to check the integrity of the data. When
EEPROM programming and verification have been finished successfully, the Transpon-
der IC enters uplink mode, transmitting the block just programmed.
The typical programming time is 18 ms.
Error Handling
Several error conditions are detected by the transponder IC to ensure that only valid
information is programmed into the EEPROM.
Errors During EEPROM
Programming
There are two types of errors which will lead to dedicated actions.
Verification error
If one of the data verification cycles fails, the transponder IC will inhibit modulation
and will not return to the uplink mode. This modulation defeat state is terminated by
re-entering the downlink mode with a start gap.
Block write protection
If the lock bit of the addressed block is set, programming is disabled. In this case,
the programming cycle is not initiated and the transponder IC reverts to uplink
mode, transmitting the currently addressed (and unmodified) block continuously.
Errors During Data
Transmission
The following errors are detected by the decoder:
Bit error
Wrong number of field clocks between two gaps (i.e., not a valid 0 or 1 pulse
stream).
Frame error
The number of data bits received is incorrect:
–
Valid bit count for 3-bit address write is 38 bits
–
Valid bit count for 5-bit address write is 40 bits
–
7 bits for a direct access command
If any of these conditions is detected, the transponder IC enters uplink mode starting
with block 1.
EEPROM Memory
Organization
The memory array of the transponder IC consists of 1,056-bits of EEPROM, arranged in
32 individually addressable blocks of 33 bits each, consisting of one lock bit and 32 data
bits. All 33 bits, including the lock bit, are programmed simultaneously.
The programming voltage is generated on-chip.
Lock Bit
Each block has an associated write lock bit that protects the entire block. By default all
lock bits L are reset (0).
Note:
Once set, the lock bit and the content of the associated block cannot be altered.
Memory Map
The configuration data of the transponder IC is stored in block 0 of the EEPROM.
The remaining 31 data blocks (1 to 31) each consist of 1 lock bit and 32 user data bits.
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