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參數(shù)資料
| 型號： | TK75018DCTL |
| 廠商： | TOKO INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHED CAPACITOR VOLTAGE CONVERTER WITH REGULATOR |
| 中文描述： | SWITCHED CAPACITOR CONVERTER, 35 kHz SWITCHING FREQ-MAX, PDIP8 |
| 封裝： | DIP-8 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 91K |
| 代理商： | TK75018DCTL |
Page 6
May 1999 TOKO, Inc.
TK75018
The illustration in Figure 2 represents an equivalent circuit
to the basic example of a switched capacitor circuit in
Figure 1.
The efficiency of the ideal converter is given by the output
power divided by the input power. Since the same current
flows out of each potential, the efficiency,
η
, is equal to the
ratio of V
2
to V
1
.
FEEDBACK AND SHUTDOWN (FB/SD)
By configuring an error voltage divider into the FB/SD pin,
the TK75018 can be used to regulate the output voltage.
It is recommended that the parallel combination of the
divider resistors be greater than approximately 16 k
due
to the limited current available from the reference. The
Error Amplifier compares the FB/SD pin against an internal
1.25 V reference and limits the charge rate of C
IN
, thereby
limiting its peak charged voltage over a given clock period
and, thus, lowering the charge delivery rate to the output.
The characteristic frequency response of the converter
can be tailored by adjusting the ratio of C
OUT
:C
IN
, but it is
recommended to keep it around 10:1. A “l(fā)ead” capacitor
from the negative output to the feedback input is required
to maintain good light-load regulation; 2000 pF is
recommended, regardless of output voltage. For standard
configurations, the magnitude of the regulated voltage
must be less than that which can be achieved without
regulation, |V
OUT
| – V
LOSS
. Higher regulated output voltages
can be achieved by configuring a voltage doubler, at the
expense of maximum available output current.
When the FB/SD pin is pulled below the shutdown threshold
of ~0.45 V (e.g., via an open collector of an NPN transistor),
the reference is shut off and the switching action is
terminated. The drivers are set to allow both C
IN
and C
OUT
to discharge into the output load. The quiescent supply
current will drop to ~ 60
μ
A. If an error voltage divider is not
THEORY OF OPERATION (CONT.)
FIGURE 2: SWITCHED CAPACITOR EQUIVALENT
CIRCUIT
IL
V1
C2
V2
REQUIV
Using equalities established above we find:
η
= V
2
/ V
1
= {V
1
– [I
L
/ (
O
x
C
1
)]} / V
1
= 1 – [I
L
/ (
O
x
C
1
x
V
1
)]
The last term in the equality string shows that efficiency
can be improved by increasing frequency or the value of
C
1
. Limitations of the circuit and components tend to cause
losses which increase with increasing frequency. Therefore,
at some point in the frequency spectrum losses will be
minimized. Hence, the oscillator of the TK75018 is designed
to run in the frequency band where losses are minimized.
Since the user will primarily be interested in maintaining a
given output voltage, losses are characterized in terms of
the voltage loss.
being used, the TK75018 will automatically restart when
the shutdown signal is removed. If such a divider is being
used, the current through the divider may be sufficient to
keep the device in shutdown until C
OUT
is fully discharged,
since the reference to the amplifier has collapsed during
the shutdown. Although C
OUT
is discharged fairly quickly
(allowing a quick restart), this recycling delay may not be
acceptable in some applications. This recycling delay can
be bypassed by injecting a positive start-up pulse into the
SD/FB pin (see Figure 3). This might be readily configured,
for example, as a TTL level signal which is diode coupled
into the divider. A resistor should be chosen to limit the
voltage pulse injection magnitude to 0.7 to 1.1 V. A pulse
width of
≥
100
μ
s is required to guarantee a successfully
coupled start-up signal.
PIN DESCRIPTIONS
FIGURE 3: FEEDBACK AND SHUTDOWN
VOUT
COUT
TA33 μF
R1
R2
4.7 μF
VIN
+
+
SHUTDOWN
CIN
TA2.2 μF
RESTART
FB/SD
CAP +
GND
CAP -
V +
VOUT
Vref
+
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