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參數(shù)資料
| 型號： | TK75050D |
| 廠商： | TOKO INC |
| 元件分類： | MOSFETs |
| 英文描述： | SMART MOSFET DRIVER |
| 中文描述： | 1.5 A BUF OR INV BASED MOSFET DRIVER, PDIP8 |
| 封裝： | DIP-8 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 131K |
| 代理商： | TK75050D |
Page 10
January 1999 TOKO, Inc.
TK75050
addition to the short-circuit protection, the board also illustrates how to use the IC for driving and protecting a floating
switch.
CIRCUIT SCHEMATIC
Figure 8 shows the circuit schematic. The operation is as follows: U
1
, a 5-pin PWM IC (TK75001) generates a 30 kHz
square-wave signal, with about 15 V peak-to-peak magnitude and 44% duty ratio. That square-wave signal is connected
to the primary winding of a pulse transformer T
1
through a coupling capacitor C
9
and a small series resistor R
11
. A voltage-
doubler comprising C
3
, C
4
, D
3
and D
4
rectifies the transformed square wave appearing across the secondary winding of
the transformer, generating a floating supply voltage of about 12 V for the MOSFET driver IC U
2
(TK75050). A drive signal
is derived for U
2
from the voltage across the diode D
4
with the help of the resistive divider R
3
and R
2
. The output of U
2
(pin 3) is connected to the gate of the MOSFET Q
1
through a 150 ohm resistor R
4
and a parallel diode D
5
. The current
of the MOSFET switch is sensed by resistor R
5
. D
6
and D
7
protect the PGND/CS pin (pin 1) of U
2
from excessive voltage;
D
8
and D
9
prevent the voltages of pins 3 and 1 from swinging below ground by more than 0.3 V. The MOSFET Q
1
is
connected to a DC-bus through a small inductor L
1
. That inductor represents the inductance of a wire connection to a
load, which is at a distance of approximately 1 meter from the MOSFET. By placing a short across jumper JP
1
, we can
emulate the case when the free-wheeling diode in a buck or boost converter fails. If the inductor L
1
is not shorted, a clamp
comprising D
10
, C
6
and R
7
limits the drain voltage excursion of Q
1
to about 60 V above the bus voltage.
A test loop is provided for clamp-on type current probes to monitor the current in the MOSFET Q
1
. Test points TP
1
through
TP
4
are available for measuring the dc bus voltage and the voltage across Q
1
.
The DC-bus is generated by rectifying the line voltage with a bridge rectifier (in the case of 230 V
RMS
line) or with a voltage
doubler (in the case of 115 V
RMS
line, when jumper JP
2
is shorted). Alternatively, a DC source of not more than 400 V
can be connected to the line terminals.
Notes: (1) Leave JP
open if you connect more than 250 V dc voltage to the line terminals, otherwise the excess voltage across C
or C
can lead
to failure of the capacitor. (2) Never operate the circuit from 230 V
RMS
line with the jumper JP
2
shorted. In such a case excess bus voltage will develop
that will destroy capacitor C
7
and C
8
and transistor Q
1
.
APPLICATION INFORMATION (CONT.)
VCC
IN
GND
PGND/CS
GND
OUT
FB
CT
GND
GND
VCC
DRV
+15 V
TP5
1 k
1N52D11
C2
C1
+
TKU1
D1
D2
C9
1
R11
10
n1
n2
T1
D4
D3
R1
10
C4
C5
0.1
+
D7
D6
R3
22 k
R2
10 k
TKU2
D8
D9
D5
R4
150
R5
1 W
Q1
HS1
D10
C6
R7
1 k
1 W
R6
10
TP3
TP1
TP2
C8
C7
R8
1 M
D14
D13
JP2
R9
1 M
D12
D15
1A F1
11Vrms
JP1
L1
FTPROBE
TP4
TEST POINT FOR VOLTAGE OBSERVATION
TEST POINT FOR
T(MAX. 400 VDC)
Q1: IRF820 (IR PREFERRED)
D3, D4, D6, D7: 1N4148
C7, C8: 2.2 , 250 V (PANASONIC SU SERIES, RADIAL, ECE-A2EU2R2)
C3
1
FIGURE 8: CIRCUIT SCHEMATIC
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