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參數(shù)資料
| 型號(hào)： | TL16PNP100APT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, QFP-48 |
| 文件頁(yè)數(shù)： | 3/21頁(yè) |
| 文件大小： | 304K |
| 代理商： | TL16PNP100APT |
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TL16PNP100A
STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER
SLLS200C – MARCH 1995 – REVISED SEPTEMBER 1997
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
2.
Program the I/O ports descriptors in the EEPROM as follows:
47h
I/O port descriptors with 7 bytes
01h
Information, bit 0 is set. The logical device is decoding full 16-bit ISA addresses
00h
Address bits 7–0 for minimum configuration base I/O address
02h
Address bits 15–8 for minimum configuration base I/O address
00h
Address bits 7–0 for maximum configuration base I/O address
03h
Address bits 15–8 for maximum configuration base I/O address
08h
Base alignment, which has a block size of 8 bytes
01h
One I/O port is needed
Using the above setup, the PnP BIOS maps the logical device to an address so that the upper six bits are always
zeros. The 0 output from the OR gate occurs when SA15-SA10 and SAEN are low. This forces the logical device
to check SA09-SA0 for a possible valid address.
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