參數(shù)資料
型號(hào): TLC1542QDBLE
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 11-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
封裝: PLASTIC, SO-20
文件頁(yè)數(shù): 7/33頁(yè)
文件大?。?/td> 525K
代理商: TLC1542QDBLE
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
timing diagrams (continued)
Access Cycle B
Shift in New Multiplexer Address;
Simultaneously Shift Out Previous
Conversion Value
Sample Cycle B
A/D Conversion
Interval
Initialize
MSB
LSB
Previous Conversion Data
MSB
LSB
B3
B2
B1
B0
C3
B9
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
12
3
4
5
6
78
9
10
1
I/O
CLOCK
DATA
OUT
ADDRESS
CS
EOC
Initialize
Low
Level
Hi-Z
See Note B
11
16
(see Note A)
NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system
clock after CS
↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the
minimum CS setup time has elapsed.
B. A low-to-high transition of CS disables ADDRESS and the I/O CLOCK within a maximum of a setup time plus two falling edges of
the internal system clock.
Figure 11. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Interval Shorter Than Conversion)
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