參數(shù)資料
型號: TLC2272QD
廠商: Texas Instruments
文件頁數(shù): 41/77頁
文件大?。?/td> 0K
描述: IC OPAMP GP R-R 2.25MHZ 8SOIC
標(biāo)準(zhǔn)包裝: 75
系列: LinCMOS™
放大器類型: 通用
電路數(shù): 2
輸出類型: 滿擺幅
轉(zhuǎn)換速率: 3.6 V/µs
增益帶寬積: 2.25MHz
電流 - 輸入偏壓: 1pA
電壓 - 輸入偏移: 300µV
電流 - 電源: 2.4mA
電流 - 輸出 / 通道: 50mA
電壓 - 電源,單路/雙路(±): 4.4 V ~ 16 V,±2.2 V ~ 8 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 管件
產(chǎn)品目錄頁面: 868 (CN2011-ZH PDF)
其它名稱: 296-7120-5
TLC227x, TLC227xA
Advanced LinCMOS RAILTORAIL
OPERATIONAL AMPLIFIERS
SLOS190G FEBRUARY 1997 REVISED MAY 2004
46
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts
, the model generation software used
with Microsim PSpice
. The Boyle macromodel (see Note 5) and subcircuit in Figure 59 were generated using
the TLC227x typical electrical and operating characteristics at TA = 25°C. Using this information, output
simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):
D Maximum positive output voltage swing
D Maximum negative output voltage swing
D Slew rate
D Quiescent power dissipation
D Input bias current
D Open-loop voltage amplification
D Unity gain frequency
D Common-mode rejection ratio
D Phase margin
D DC output resistance
D AC output resistance
D Short-circuit output current limit
NOTE 5: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers”, IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
OUT
+
+
+
+
+
+
+
+
+
.SUBCKT TLC227x 1 2 3 4 5
C1
11
1214E12
C2
6
760.00E12
DC
5
53DX
DE
54
5DX
DLP
90
91DX
DLN
92
90DX
DP
4
3DX
EGND
99
0POLY (2) (3,0) (4,) 0 .5 .5
FB
99
0POLY (5) VB VC VE VLP VLN 0
+ 984.9E3 1E6 1E6 1E6 1E6
GA
6
011 12 377.0E6
GCM 0 6 10 99 134E9
ISS
3
10DC 216.OE6
HLIM
90
0VLIM 1K
J1
11
210 JX
J2
12
110 JX
R2
6
9100.OE3
RD1
60
112.653E3
RD2
60
122.653E3
R01
8
550
R02
7
9950
RP
3
44.310E3
RSS
10
99925.9E3
VAD
60
4.5
VB
9
0DC 0
VC 3 53 DC .78
VE
54
4DC .78
VLIM
7
8DC 0
VLP
91
0DC 1.9
VLN
0
92DC 9.4
.MODEL DX D (IS=800.0E18)
.MODEL JX PJF (IS=1.500E12BETA=1.316E-3
+ VTO=.270)
.ENDS
VCC +
RP
IN
2
IN +
1
VCC
VAD
RD1
11
J1
J2
10
RSS
ISS
3
12
RD2
60
VE
54
DE
DP
VC
DC
4
C1
53
R2
6
9
EGND
VB
FB
C2
GCM
GA
VLIM
8
5
RO1
RO2
HLIM
90
DIP
91
DIN
92
VIN
VIP
99
7
Figure 59. Boyle Macromodel and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
Macromodels, simulation models, or other models provided by TI,
directly or indirectly, are not warranted by TI as fully representing all
of the specification and operating characteristics of the
semiconductor product to which the model relates.
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