參數(shù)資料
    

    


    


    
型號(hào)：
TLC2543CDB

    

    
廠商：
TEXAS INSTRUMENTS INC

    

    
元件分類：
ADC

    

    
英文描述：
11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20

    

    
封裝：
GREEN, PLASTIC, SSOP-20

    

    
文件頁(yè)數(shù)：
7/32頁(yè)

    

    
文件大小：
804K

    

    
代理商：
TLC2543CDB


    

    

    

	
    
    
    

    
    
	
    TLC2543C, TLC2543I, TLC2543M
    12-BIT ANALOG-TO-DIGITAL CONVERTERS
    WITH SERIAL CONTROL AND 11 ANALOG INPUTS
    SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001
    15
    POST OFFICE BOX 655303
     DALLAS, TEXAS 75265
    PRINCIPLES OF OPERATION
    data output length
    The next two bits (D3 and D2) of the data register select the output data length. The data-length selection is
    valid for the current I/O cycle (the cycle in which the data is read). The data-length selection, being valid for the
    current I/O cycle, allows device start-up without losing I/O synchronization. A data length of 8, 12, or 16 bits can
    be selected. Since the converter has 12-bit resolution, a data length of 12 bits is suggested.
    With D3 and D2 set to 00 or 10, the device is in the 12-bit data-length mode and the result of the current
    conversion is output as a 12-bit serial data stream during the next I/O cycle. The current I/O cycle must be exactly
    12 bits long for proper synchronization, even when this means corrupting the output data from a previous
    conversion. The current conversion is started immediately after the twelfth falling edge of the current I/O cycle.
    With bits D3 and D2 set to 11, the 16-bit data-length mode is selected, which allows convenient communication
    with 16-bit serial interfaces. In the 16-bit mode, the result of the current conversion is output as a 16-bit serial
    data stream during the next I/O cycle with the four LSBs always reset to 0 (pad bits). The current I/O cycle must
    be exactly 16 bits long to maintain synchronization even when this means corrupting the output data from the
    previous conversion. The current conversion is started immediately after the sixteenth falling edge of the current
    I/O cycle.
    With bits D3 and D2 set to 01, the 8-bit data-length mode is selected, which allows fast communication with 8-bit
    serial interfaces. In the 8-bit mode, the result of the current conversion is output as an 8-bit serial data stream
    during the next I/O cycle. The current I/O cycle must be exactly eight bits long to maintain synchronization, even
    when this means corrupting the output data from the previous conversion. The four LSBs of the conversion
    result are truncated and discarded. The current conversion is started immediately after the eighth falling edge
    of the current I/O cycle.
    Since D3 and D2 take effect on the current I/O cycle when the data length is programmed, there can be a conflict
    with the previous cycle when the data-word length is changed from one cycle to the next. This may occur when
    the data format is selected to be least significant bit first, since at the time the data length change becomes
    effective (six rising edges of I/O CLOCK), the previous conversion result has already started shifting out.
    In actual operation, when different data lengths are required within an application and the data length is changed
    between two conversions, no more than one conversion result can be corrupted and only when it is shifted out
    in LSB-first format.
    sampling period
    During the sampling period, one of the analog inputs is internally connected to the capacitor array of the
    converter to store the analog input signal. The converter starts sampling the selected input immediately after
    the four address bits have been clocked into the input data register. Sampling starts on the fourth falling edge
    of I/O CLOCK. The converter remains in the sampling mode until the eighth, twelfth, or sixteenth falling edge
    of the I/O CLOCK depending on the data-length selection. After the EOC delay time from the last I/O CLOCK
    falling edge, the EOC output goes low indicating that the sampling period is over and the conversion period has
    begun. After EOC goes low, the analog input can be changed without affecting the conversion result. Since the
    delay from the falling edge of the last I/O CLOCK to EOC low is fixed, time-varying analog input signals can be
    digitized at a fixed rate without introducing systematic harmonic distortion or noise due to timing uncertainty.
    After the 8-bit data stream has been clocked in, DATA INPUT should be held at a fixed digital level until EOC
    goes high (indicating that the conversion is complete) to maximize the sampling accuracy and minimize the
    influence of external digital noise.
    
    
    
    
    
    


    


    

    相關(guān)PDF資料
    		

    PDF描述
    		

    
    

    
TLC2543IDWR
11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20

    

    
TLC2543IDW
11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20

    

    
TLC2543MJ
11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP20

    

    
TLC2543CDBG4
11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20

    

    
TLC2543CDBRG4
11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20

    

    

    

    


    


    

    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
TLC2543CDB
 制造商:Texas Instruments 功能描述:A/D Converter (A-D) IC

    

    
TLC2543CDBG4
功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12Bit 66kSPS Ser Out Prog MSB/LSB First RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32

    

    
TLC2543CDBR
功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12Bit 66kSPS Ser Out Prog MSB/LSB First RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32

    

    
TLC2543CDBRG4
功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12Bit 66kSPS Ser Out Prog MSB/LSB First RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32

    

    
TLC2543CDW
功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12bit ADC w/11 Ch RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32

    

    
    
    
    
	
    	
    
    
     
     
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