參數(shù)資料
型號: TLC2543I
廠商: Texas Instruments, Inc.
英文描述: 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
中文描述: 12位模擬數(shù)字轉(zhuǎn)換器與串行控制和11個模擬輸入
文件頁數(shù): 19/27頁
文件大?。?/td> 431K
代理商: TLC2543I
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D – DECEMBER 1993 – REVISED MAY 1997
19
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
converter and analog input
The CMOS threshold detector in the successive-approximation conversion system determines each bit by
examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase of the
conversion process, the analog input is sampled by closing the S
C
switch and all S
T
switches simultaneously.
This action charges all the capacitors to the input voltage.
In the next phase of the conversion process, all S
T
and S
C
switches are opened and the threshold detector
begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF–)
voltage. In the switching sequence, 12 capacitors are examined separately until all 12 bits are identified and
the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector looks
at the first capacitor (weight = 4096). Node 4096 of this capacitor is switched to the REF+ voltage, and the
equivalent nodes of all the other capacitors on the ladder are switched to REF–. When the voltage at the
summing node is greater than the trip point of the threshold detector (approximately 1/2 V
CC
), a bit 0 is placed
in the output register and the 4096-weight capacitor is switched to REF–. When the voltage at the summing node
is less than the trip point of the threshold detector, a bit 1 is placed in the register and this 4096-weight capacitor
remains connected to REF+ through the remainder of the successive-approximation process. The process is
repeated for the 2048-weight capacitor, the 1024-weight capacitor, and so forth down the line until all bits are
determined. With each step of the successive-approximation process, the initial charge is redistributed among
the capacitors. The conversion process relies on charge redistribution to determine the bits from MSB to LSB.
reference voltage inputs
The two reference inputs used with the device are the voltages applied to the REF+ and REF– terminals. These
voltage values establish the upper and lower limits of the analog input to produce a full-scale and zero-scale
reading respectively. These voltages and the analog input should not exceed the positive supply or be lower
than ground consistent with the specified absolute maximum ratings. The digital output is at full scale when the
input signal is equal to or higher than REF+ terminal voltage and at zero when the input signal is equal to or lower
than REF– terminal voltage.
SC
Threshold
Detector
Node 4096
REF–
REF+
ST
4096
VI
To Output
Latches
REF–
ST
REF+
REF–
ST
REF+
REF–
ST
REF+
REF–
ST
REF+
REF–
ST
REF+
REF–
ST
REF+
REF–
ST
REF–
ST
1
1
2
4
8
16
1024
2048
Figure 15. Simplified Model of the Successive-Approximation System
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