參數(shù)資料
型號: TLC2543QDWREP
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
封裝: GREEN, PLASTIC, SOIC-20
文件頁數(shù): 2/28頁
文件大小: 524K
代理商: TLC2543QDWREP
www.ti.com
Access Cycle B
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
Sample Cycle B
A/D Conversion
Interval
Initialize
MSB
LSB
Previous Conversion Data
MSB
LSB
B7
B6
B5
B4
C7
B7
A7
A6
A5
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
8
1
I/O CLOCK
DATA OUT
DATA INPUT
CS
EOC
Initialize
Hi-Z
(see Note A)
B3
B2
B1
B0
t(conv)
Access Cycle B
Sample Cycle B
A/D Conversion
Interval
Initialize
MSB
LSB
Previous Conversion Data
MSB
LSB
B7
B6
B5
B4
C7
B7
A7
A6
A5
A4
A3
A2
A1
A0
Low Level
1
2
3
4
5
6
7
8
1
I/O CLOCK
DATA OUT
DATA INPUT
CS
EOC
Initialize
(see Note A)
B3
B2
B1
B0
t(conv)
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
12-BIT ANALOG-TO-DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SGLS125A – JULY 2002 – REVISED NOVEMBER 2006
A.
To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS
↓ before responding to
control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time
has elapsed.
Figure 11. Timing for 8-Clock Transfer Using CS With MSB First
A.
To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS
↓ before responding to
control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time
has elapsed.
Figure 12. Timing for 8-Clock Transfer Not Using CS With MSB First
10
相關(guān)PDF資料
PDF描述
TLC2543MFK 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CQCC20
TLC2552IDGK 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
TLC2552IDR 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
TLC2555IDGK 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
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