參數(shù)資料
型號(hào)： TLC32040M
廠商： Texas Instruments, Inc.
英文描述： ANALOG INTERFACE CIRCUIT
中文描述： 模擬接口電路
文件頁(yè)數(shù)： 8/30頁(yè)
文件大?。?/td> 202K
代理商： TLC32040M
|
|
Control Register
TLC32040M
ANALOG INTERFACE CIRCUIT
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
4–8
secondary DX serial communication protocol
x x |
←
to TA register
→
| x x |
←
to RA register
→
| 0 0
x |
←
to TA’ register
→
| x |
←
to RA’ register
→
| 0 1
x |
←
to TB register
→
| x |
←
to RB register
→
| 1 0
x x x x x x x x d7 d6 d5 d4 d3 d2 1 1
d13 and d6 are MSBs (unsigned binary)
d14 and d7 are 2s complement sign bits
d14 and d7 are MSBs (unsigned binary)
d2 = 0/1 deletes/inserts the band-pass filter
d3 = 0/1 disables/enables the loopback function
d4 = 0/1 disables/enables the AUX IN+ and AUX IN– terminals
d5 = 0/1 asynchronous/synchronous transmit and receive sections
d6 = 0/1 gain control bits (see gain control section)
d7 = 0/1 gain control bits (see gain control section)
reset function
A reset function is provided to initiate serial communications between the AIC and DSP. The reset function will
initialize all AIC registers, including the control register. After power has been applied to the AIC, a
negative-going pulse on RESET will initialize the AIC registers to provide an 8-kHz A/D and D/A conversion
rate for a 5.184-MHz master clock input signal. The AIC, except the control register, will be initialized as follows
(see AIC DX data word format section):
INITIALIZED
REGISTER
VALUE (HEX)
REGISTER
TA
TA’
9
1
TB
24
RA
9
RA’
1
RB
24
The control register bits will be reset as follows (see AIC DX data word format section):
d7 = 1, d6 = 1, d5 = 1, d4 = 0, d3 = 0, d2 = 1
This initialization allows normal serial port communications to occur between the AIC and DSP. If the transmit
and receive sections are configured to operate synchronously and the user wishes to program different
conversion rates, only the TA, TA’, and TB registers need to be programmed, since both transmit and receive
timing are synchronously derived from these registers (see the Terminal Functions table and AIC DX data word
format section).
The circuit shown below provides a reset on power up when power is applied in the sequence given under
power-up sequence. The circuit depends on the power supplies’ reaching their recommended values a
minimum of 800 ns before the capacitor charges to 0.8 V above DGTL GND.
VCC+
RESET
5 V
–5 V
0.5
μ
F
200 k
VCC–
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