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參數(shù)資料
| 型號(hào)： | TLC32040MJ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ANALOG INTERFACE CIRCUIT |
| 中文描述： | 模擬接口電路 |
| 文件頁數(shù)： | 17/30頁 |
| 文件大?。?/td> | 202K |
| 代理商： | TLC32040MJ |
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ANALOG INPUT
±
6 V
Half scale
±
3 V
Full scale
INPUT CONFIGURATIONS
TLC32040M
ANALOG INTERFACE CIRCUIT
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
4–17
Table 2. Gain Control Table
(Analog Input Signal Required for Full-Scale A/D Conversion)
CONTROL REGISTER BITS
d6
1
0
1
0
1
0
1
0
A/D CONVERSION
RESULT
d7
1
0
0
1
1
0
0
1
Differential configuration
Analog input = IN+ – IN–
= AUX IN+ – AUX IN–
±
3 V
±
1.5 V
Full scale
Full scale
Single-ended configuration
Analog input = IN+ – ANLG GND
= AUX IN+ – ANLG GND
±
3 V
±
1.5 V
Full scale
Full scale
In this example, Vref is assumed to be 3 V. In order to minimize distortion, it is recommended that the analog input not exceed
0.1 dB below full scale.
+
–
To MUX
R
IN +
IN –
–
+
R
R
+
–
AUX IN –
AUX IN +
R
To MUX
Rfb
+
–
Rfb = R for d6 = 1, d7 = 1
d6 = 0, d7 = 0
Rfb = 2R for d6 = 1, d7 = 0
Rfb = 4R for d6 = 0, d7 = 1
Rfb
Rfb
Rfb
Rfb = R for d6 = 1, d7 = 1
d6 = 0, d7 = 0
Rfb = 2R for d6 = 1, d7 = 0
Rfb = 4R for d6 = 0, d7 = 1
Figure 1. IN+ and IN– Gain
Control Circuitry
Figure 2. AUX IN+ and AUX IN–
Gain Control Circuitry
(sin x)/x correction section
The AIC does not have (sin x)/x correction circuitry after the digital-to-analog converter. (sin x)/x correction can
be accomplished easily and efficiently in digital signal processor (DSP) software. Excellent correction accuracy
can be achieved to a band edge of 3000 Hz by using a first-order digital correction filter. The results, which are
shown on the next page, are typical of the numerical correction accuracy that can be achieved for sample rates
of interest. The filter requires only seven instruction cycles per sample on the SMJ320 DSPs. With a 200-ns
instruction cycle, nine instructions per sample represents an overhead factor of 1.4% and 1.7% for sampling
rates of 8000 Hz and 9600 Hz, respectively. This correction will add a slight amount of group delay at the upper
edge of the 300 – 3000-Hz band.
(sin x)/x roll-off for a zero-order hold function
The (sin x)/x roll-off for the AIC DAC zero-order hold function at a band-edge frequency of 3000 Hz for the various
sampling rates is shown in the following table.
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