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參數(shù)資料
| 型號： | TLC32046C |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Wide-Band Analog Interface Circuit |
| 中文描述： | 寬帶模擬接口電路 |
| 文件頁數(shù)： | 14/57頁 |
| 文件大?。?/td> | 297K |
| 代理商： | TLC32046C |
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1–8
1.5
Terminal Functions (continued)
TERMINAL
NAME
NO.
DGTL
9
DESCRIPTION
I/O
Digital ground for all internal logic circuits. Not internally connected to ANLG GND.
FSD
1
O
Frame sync data. The FSD output remains high during primary communication. In the
dual-word (telephone interface) mode, FSD is identical to FSX during secondary
communication.
WORD-BYTE
I
WORD-BYTE allows differentiation between the word and byte data format (see
DATA-DR/CONTROL and Table 2-1 for details).
FSR
4
O
Frame sync receive. FSR is held low during bit transmission. When FSR goes low, the
TMS320 serial port begins receiving bits from the AIC via DR of the AIC. The most
significant DR bit is present on DR before FSR goes low (see Serial Port Sections and
Internal Timing Configuration Diagrams).
FSX
14
O
Frame sync transmit. When FSX goes low, the TMS320 serial port begins transmitting
bits to the AIC via DX of the AIC. FSX is held low during bit transmission (see Serial Port
Sections and Internal Timing Configuration Diagrams).
IN+
26
I
Noninverting input to analog input amplifier stage
IN–
25
I
Inverting input to analog input amplifier stage
MSTR CLK
6
I
The master clock signal is used to derive all the key logic signals of the AIC, such as
the shift clock, the switched-capacitor filter clocks, and the A/D and D/A timing signals.
The Internal Timing Configuration diagram shows how these key signals are derived.
The frequencies of these signals are synchronous submultiples of the master clock
frequency to eliminate unwanted aliasing when the sampled analog signals are
transferred between the switched-capacitor filters and the ADC and DAC converters
(see the Internal Timing Configuration).
OUT+
22
O
Noninverting output of analog output power amplifier. OUT+ drives transformer hybrids
or high-impedance loads directly in a differential or a single-ended configuration.
OUT–
21
O
Inverting output of analog output power amplifier. OUT– is functionally identical with and
complementary to OUT+.
REF
8
I/O
The internal voltage reference is brought out on REF. An external voltage reference can
be applied to REF to override the internal voltage reference.
RESET
2
I
A reset function is provided to initialize TA, TA’, TB, RA, RA’, RB (see Figure 2-1), and
the control registers. This reset function initiates serial communications between the
AIC and DSP. The reset function initializes all AIC registers, including the control
register. After a negative-going pulse on RESET, the AIC registers are initialized to
provide a 16-kHz data conversion rate for a 10.368-MHz master clock input signal. The
conversion rate adjust registers, TA’ and RA’, are reset to 1. The CONTROL register bits
are reset as follows (see AIC DX Data Word Format section):
D11 = 0, D10 = 0, D9 = 1, D7 = 1, D6 = 1, D5 = 1, D4 = 0, D3 = 0, D2 = 1
The shift clock (SCLK) is held high during RESET.
This initialization allows normal serial-port communication to occur between the AIC
and the DSP.
SHIFT CLK
10
O
The shift clock signal is obtained by dividing the master clock signal frequency by four.
SHIFT CLK is used to clock the serial data transfers of the AIC.
VDD
VCC+
VCC–
7
Digital supply voltage, 5 V
±
5%
Positive analog supply voltage, 5 V
±
5%
Negative analog supply voltage, –5 V
±
5%
20
19
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