- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383953 > TLC320AC02C (Texas Instruments, Inc.) RB Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 05V; Output Voltage (Vdc): 24V; Power: 1W; Low Cost 1W Converter; Power Sharing on Dual Output Version; Industry Standard Pinout; 1kVDC & 2kVDC Isolation Options; Optional Continuous Short Circuit Protected; UL94V-0 Package Material; Efficiency to 85% PDF資料下載
參數(shù)資料
| 型號： | TLC320AC02C |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | DC/DC變換器 |
| 英文描述： | RB Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 05V; Output Voltage (Vdc): 24V; Power: 1W; Low Cost 1W Converter; Power Sharing on Dual Output Version; Industry Standard Pinout; 1kVDC & 2kVDC Isolation Options; Optional Continuous Short Circuit Protected; UL94V-0 Package Material; Efficiency to 85% |
| 中文描述： | 單電源模擬接口電路 |
| 文件頁數(shù)： | 71/84頁 |
| 文件大?。?/td> | 447K |
| 代理商： | TLC320AC02C |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁當(dāng)前第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁
A–1
Appendix A
Primary Control Bits
The function of the primary-word control bits D01 and D00 and the hardware terminals FC0 and FC1 are
shown below. Any combinational state of D01, D00, FC1, and FC0 not shown is ignored.
CONTROL FUNCTION OF CONTROL BITS
BITS
TERMINALS
FC1
D01
D00
FC0
0
0
0
0
On the next falling edge of FS, the AIC receives DAC data D15–D02 to DIN and
transmits the ADC data D15–D00 from DOUT.
0
0
0
1
On the next falling edge of FS, the AIC receives DAC data D15–D02 to DIN and
transmits the ADC data D15–D00 from DOUT.
The phase adjustment is determined by the state of FC1 and FC0 such that on the
next rising edge of the next internal FS, the next ADC/DAC sampling time occurs later
by the number of MCLK periods equal to the value contained in the A
′
register. When
the A
′
register value is negative, the internal falling edge of FS occurs earlier.
On the next falling edge of FS, the AIC receives DAC data D15–D02 at DIN and
transmits the ADC data D15–D00 from DOUT.
0
0
1
0
The phase adjustment is determined by the state of FC1 and FC0 such that on the
rising edge of the next internal FS, the next ADC/DAC sample time occurs earlier by
the number of MCLK periods determined by the value contained in the A
′
register.
When the A
′
register value is negative, the internal falling edge of FS occurs later.
On the next falling edge of the primary FS, the AIC receives DAC data D15–D02 at
DIN and transmits the ADC data D15–D00 from DOUT.
0
0
1
1
When FC0 and FC1 are both taken high, the AIC initiates a secondary FS to receive
a secondary control word at DIN. The secondary frame sync occurs at 1/2 the
sampling time as measured from the falling edge of the primary FS.
0
1
0
0
On the next falling edge of FS, the AIC receives DAC data D15–D02 to DIN and
transmits the ADC data D15–D00 from DOUT.
The phase adjustment is determined by the state of D01 and D00 such that on the
next rising edge of FS, the next ADC/DAC sampling time occurs later by the number
of MCLK periods determined by the value contained in the A
′
register. When the A
′
register value is negative, the falling edge of FS occurs earlier.
1
0
0
0
On the next falling edge of FS, the AIC receives DAC data D15–D02 at DIN and
transmits the ADC data D15–D00 from DOUT.
The phase adjustment is determined by the state of D01 and D00. On the next rising
edge of FS, the next ADC/DAC sampling time occurs earlier by the number of MCLK
periods determined by the value contained in the A
′
register. When the A
′
register
value is negative, the internal falling edge of FS occurs later.
1
1
0
0
On the next falling edge of FS, the AIC receives DAC data D15–D02 to DIN and
transmits the ADC data D15–D00 from DOUT.
When D00 and D01 are both high, the AIC initiates a secondary FS to receive a
secondary control word at DIN. The secondary frame sync occurs at 1/2 the sampling
time as measured from the falling edge of the primary FS.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TLC320AC01C | Single-Supply Analog Interface Circuit |
| TLC320AD50C | SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION |
| TLC320AD50C-I | SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION |
| TLC320AD50I | SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION |
| TLC320AD535C | DUAL CHANNEL VOICE/DATA CODEC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLC320AC02CFN | 功能描述:接口—CODEC SNGL CH Codec Bandwidth Indpendent RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLC320AC02CFNR | 功能描述:接口—CODEC SNGL CH Codec Bandwidth Indpendent RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLC320AC02CPM | 功能描述:接口—CODEC SNGL CH Codec Bandwidth Indpendent RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLC320AC02I | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Single-Supply Analog Interface Circuit |
| TLC320AC02IFN | 功能描述:接口—CODEC SNGL CH Codec Bandwidth Indpendent RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。